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? 2014 microchip technology inc. ds20005281a-page 1 feat ure s : ? i n put v o l t ag e: 4 . 5v t o 4 2 v ? c an be co nfi gur ed w i th m ul t ip le t op ol ogi es incl ud ing bu t no t li mi ted to: -f l y b a c k - ? uk -b o o s t - sepi c (sing l e - ende d pri m a r y - i ndu c t o r c o nv er t e r ) ? c ap ab le of q ua s i - r eso na nt o r fix ed - freq ue ncy op era t io n ? l ow q u ie sc en t c u rre nt: 5 m a t y pi ca l ? l o w s l ee p c u r r e nt : 30 a t y pi ca l ? l ow -sid e g a te d r iv ers : - + 5 v g a te driv e - 0 .5a si nk /sou rc e curren t -+ 1 0 v g a t e dr i v e - 1 a sin k /so u rc e c u r r ent ? p ea k c u r r e nt mo d e co nt r o l ? d i f fe rent ial rem o te o u tpu t sen s e ? m ul tipl e o u t put sys t em s : - m as ter or sl ave ? c on fig u ra ble para m e ters : -v re f , prec i s io n i ou t /v ou t set po i n t (dac) - i n put u nde rvo l t a ge loc ko ut (u v l o ) - i n put o v ervo l t ag e l o c k ou t (o vlo ) - d et ec tion an d pro t ec tio n - p ri ma ry c u rren t le adi ng edge bla n k i ng (0, 5 0 ns , 1 00 ns and 20 0 n s) - g ate dr iv e d e ad t i m e (1 6 n s to 25 6 n s) - f i x e d sw i t ch ing fre que nc y r a nge : 3 1 .25 k h z to 2.0 m hz - s l ope co m pen sa tio n - q u as i - r es on an t co n f i gu r at i o n w i t h b u il t - in c o m p arato r an d pro g ra mm abl e o f fse t v o lt a ge ad ju stm e n t - p ri m a ry cu rren t of fs et ad ju s t m e n t - c on fig ura ble g p io pin op tio ns ? i n t eg rate d lo w - sid e d i f f er enti a l c u rren t sense am pl ifi e r ? 5% cu rre nt r e gu lati on ? th e rm al shu t dow n mic r ocont rol l er feat ure s : ? p r e ci sio n 8 m h z int e r n a l o s cil la t or b l oc k: - f a c to ry-c al ibr a ted to 1 %, typ i c a l ? i nt e r r up t capa bl e -f i r m w a r e - in terru pt-o n-c h a nge pin s ? o nl y 3 5 in str u ct ion s t o l ear n ? 4 0 9 6 w o rds on-chi p pro g ram m e m o ry ? h ig h en dura n c e f l as h: - 1 00 , 00 0 w r i t e f l as h e n du r a nc e - f l a s h re t ent ion : >4 0 y ears ? w a t ch dog t i m e r ( w d t ) w i th in dep en den t o s c i l l at or fo r r e l i ab le op erat ion ? p ro gram m abl e c o d e pro t ec tio n ? i n - circ uit seria l pro g ram m i ng ? (icsp?) v i a t w o pi ns ? e i ght i/o pin s a nd on e i n pu t-on ly pin - t w o o pen d r ai n pins ? a n a lo g-to -digi t al c onv ert e r (ad c ) : - 1 0 -bi t res o l u tio n - f i v e ext e rna l c hannels ? t i m er 0: 8 - bit t i m e r/c o unt er w i t h 8-bi t pres ca ler ? e n han ce d t i m er1 : - 1 6 - bi t t i m e r w i th pr es cal e r - t w o sel e c t ab le c l oc k so urc e s ? t i m er 2: 8 - bit t i me r with pres c a le r - 8 - b it perio d r e gis t er ? i 2 c tm co m m uni ca tion : - 7 - b i t a d d r es s ma sk in g - t w o de di ca t e d a d dr e s s re g i st e r s mcp191 14/5 di gita lly en ha nce d po we r an alog synchronous low-side pwm controller http:///
MCP19114/5 ds20005281a-page 2 ? 2014 microchip technology inc. pi n di agram ? 24- pin qfn ( m cp19 1 14) MCP19114 1 2 3 4 5 6 13 7 8 9 10 11 12 14 15 16 17 18 23 22 21 20 19 24 exp-25 g p a0/ an 0 / t est _out gp a 1 /an1/ c l kpin gp a2/an2/ t 0cki/ i nt gp a 3 / a n3 gp a7/scl/ i cspclk gp a6 /ccd/icspda t gp a 5 / m c l r /test_en gpb0/sda desat n desat p /i sout i sp i sn i p a gn d p gn d sdr v pdr v v dr gpb1 / a n4 /vref2 i co m p i fb v s v in v dd http:///
? 2014 microchip technology inc. ds20005281a-page 3 mcp191 14/5 t able 1 : 24-p i n s u mm ary i/o 24-pin qfn ansel a/d timers mssp interrupt pull-up ba sic a dditi onal gpa0 1 y an0 ? ? ioc y ? analog/digital debug output ( 1 ) gpa1 2 y an1 ? ? ioc y ? sync signal in/out ( 2 ) gpa2 3 y an2 t0cki ? io c int y ? ? gpa3 4 y an3 ? ? ioc y ? ? gpa5 7 n ? ? ? ioc ( 4 ) y ( 5 ) mclr test enable input gpa6 6 n ? ? ? ioc y icspdat dual capture/compare input gpa7 5 n ? ? scl ioc n icspclk ? gpb0 8 n ? ? sda ioc n ? ? gpb1 24 y an4 ? ? ioc y ? v ref2 ( 3 ) desat n 9 n ? ? ? ? ? ? desat negative input desat p / i sout 10 n ? ? ? ? ? ? desa t p in put or i so u t output ( 6 ) i sp 11 n ? ? ? ? y ? c u rren t sens e am pli f ie r po si tiv e input i sn 12 n ? ? ? ? ? ? c u rr ent se ns e am pl ifi e r negative input i p 13 n ? ? ? ? ? ? primary input current sense a gnd 14 n ? ? ? ? ? a gnd small signal ground p gnd 15 n ? ? ? ? ? p gnd large signal ground sdrv 16 n ? ? ? ? ? ? se co nda ry l s g a te driv e output pdrv 17 n ? ? ? ? ? ? p r im ar y ls ga t e d r i v e output v dr 18 n ? ? ? ? ? v dr gate drive supply voltage v dd 19 n ? ? ? ? ? v dd v dd output v in 20 n ? ? ? ? ? v in input supply voltage v s 21 n ? ? ? ? ? ? output voltage sense i fb 22 n ? ? ? ? ? ? error amplifier feedback input i comp 23 n ? ? ? ? ? ? error am p lifi e r out p ut note 1 : th e an alo g /di g it al d e bu g outp ut i s s e l e c ted thro ugh the c ontr o l o f th e abecon reg i s ter . 2: selec t ed w hen fun c ti on ing as ma ste r or s l a v e by p r op er c onfi g u r ati on o f the msc < 1:0 > bi t s i n th e m o de co n r e g i s t e r . 3: v re f 2 ou tput s e l e c t ed w h e n co nfi gure d as m a s t er b y pro per c onf igu r ati on of th e ms c < 1:0 > bit s in th e m o de co n r e g i s t e r . 4: th e i o c i s d i s abl ed w hen mc l r is en abl ed. 5: w eak pull-up always enabled when mclr is en abl ed, oth e rw is e the pul l-up is un de r us er c o n t rol. 6: w hen rfb of modecon<5> = 0 , internal feedback resistor and desat p input are enabled. when rfb = 1 , i sout is enabled. http:///
MCP19114/5 ds20005281a-page 4 ? 2014 microchip technology inc. pi n di agram ? 28- pin qfn ( m cp19 1 15) mcp19115 1 2 3 4 5 6 71 5 8 9 10 11 12 13 14 16 17 18 19 20 21 26 25 24 23 22 28 27 exp-29 gp a1 /an1/cl kpin g p a2/ a n2/t0 c ki/int g p b4/an5/ i cspda t gp a 3 / a n3 gp a7 / s cl gp a 6 / c c d g p a 0 /an0/t est_o ut gpb6/an7 g pb5 /an6/i c s pc l k gpb1 / a n4 /vref2 i co m p i fb v s v in v dd v dr pdr v sdr v p gn d a gn d i p gp a5 / m cl r /test_en gpb7_ccd gpb0/sda desat n desat p /i sout i sp i sn http:///
? 2014 microchip technology inc. ds20005281a-page 5 mcp191 14/5 t able 2 : 28-p i n s u mm ary i/o 28-pin qfn ansel a/d timers mssp interrupt pull-up ba sic a ddit i ona l gpa0 1 y an0 ? ? ioc y ? analog/digital debug output ( 1 ) gpa1 2 y an1 ? ? ioc y ? sync signal in/out ( 2 ) gpa2 3 y an2 t0cki ? io c int y ? ? gpa3 5 y an3 ? ? ioc y ? ? gpa5 8 n ? ? ? ioc ( 4 ) y ( 5 ) mclr test enable input gpa6 7 n ? ? ? ioc y ? d u al c a pt u r e/ s i ng l e c om p ar e1 i npu t gp a7 6 n ? ? scl io c n ? ? g pb0 10 n ? ? sda io c n ? ? g pb1 26 y an4 ? ? io c y ? v ref2 ( 3 ) gpb4 4 y an5 ? ? io c y icspda t ? g pb5 27 y an6 ? ? io c y icspclk ? g pb6 28 y an7 ? ? io c y ? ? g pb7 9 y ? ? ? io c y ? si ngle compare2 input desa t p / i sout 12 n ? ? ? ? ? ? desa t p inpu t or i so u t ou tput ( 6 ) desa t n 11 n ? ? ? ? ? ? d esat negative input i sp 13 n ? ? ? ? y ? c u rrent sen s e am p lif ier non- inverting input i sn 14 n ? ? ? ? ? ? c u rrent sen s e am p lif ier in verting input i p 15 n ? ? ? ? ? ? pri mary input current sense a gn d 16 n ? ? ? ? ? a gn d sm all signal ground p gn d 17 n ? ? ? ? ? p gn d la rge signal ground sdrv 18 n ? ? ? ? ? ? se co nda ry ls g a te d r iv e o utput pdrv 19 n ? ? ? ? ? ? pri mary ls gate drive output v dr 20 n ? ? ? ? ? v dr g ate drive supply voltage v dd 21 n ? ? ? ? ? v dd v dd output v in 22 n ? ? ? ? ? v in inp ut supply voltage v s 23 n ? ? ? ? ? ? ou tput voltage sense i fb 24 n ? ? ? ? ? ? error amplifier feedback input i comp 25 n ? ? ? ? ? ? error am p lif ier o u tpu t note 1 : th e an alo g /di g it al d e bu g outp ut i s s e l e c ted thro ugh the c ontr o l o f th e abecon reg i s ter . 2: se lec t ed w h e n func ti oni ng as m a s t er or s l a v e by p r ope r c onf igu r ati on of the m s c < 1:0 > b i t s i n t h e m o de co n r e g i s t e r . 3: vr ef2 o u tp ut se lect e d w h en c onf igu r ed as mas t e r b y pro per co nfi gura t io n of the m s c < 1 : 0> bi t s in t h e m o de co n r e g i s t e r . 4: th e i o c i s d i s abl ed w hen mc l r is en abl ed. 5: w e a k p ull-up always enabled when mclr is en abl ed, oth e rw is e the pul l-up is un de r us er c o n t rol. 6: w hen r f b of modecon<6> =0 internal feedback resistor is enabled allow with desat p input. when rfb=1, i sout is enabled. http:///
MCP19114/5 ds20005281a-page 6 ? 2014 microchip technology inc. t a ble of conte n t s 1. 0 d evice o verv i ew .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. . . . .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. . 9 2 . 0 p in de scr i p tio n . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. . . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 3. 0 f u n ct ional descr i p t i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 9 4 . 0 e le ct r i ca l ch a r a cte r i st ic s . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 2 5 . 0 dig it a l ele ctr ic a l ch a r a cte r i st ic s . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 9 6 . 0 c o n fi g u r i n g th e m c p 1 9 1 1 4 / 5 .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 3 7 7 . 0 t yp ic a l p e r f o r m a n ce cu r ve s . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 3 8 . 0 s y st e m be n ch t e s t in g . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 7 9 . 0 d e vic e ca lib r a t i o n .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 9 10. 0 m em ory o r ganizat i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 7 1 1 . 0 de vi ce co n f i g u r a t io n ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 9 12. 0 o scillat o r mo des . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. . . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 1 1 3 . 0 r e se t s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 3 1 4 . 0 i n te r r u p t s .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 1 15. 0 p ower -down mode (sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 9 16. 0 w at chdog t i mer (w dt ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 0 1 1 7 . 0 f la s h pr o g r a m m e m o r y co n t r o l .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 0 3 1 8 . 0 i /o po r t s . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 0 9 19. 0 i nt errupt -o n-change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. . 1 1 9 20. 0 i nt ernal t e mper at ure i ndi c a t o r m odule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 2 3 21. 0 a nalog-t o -digit a l conver t e r (a dc) m odule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 2 5 22. 0 t imer 0 m odule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 5 23. 0 t imer 1 m odule wit h g a t e cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 7 24. 0 t imer 2 m odule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 4 1 25. 0 e nhanc ed p w m module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 4 3 26. 0 d ual cap t ure/ compare ( ccd) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 4 7 27. 0 p w m cont rol logi c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 1 28.0 m as t e r sy nchronous s e rial p o rt (m ssp ) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 3 2 9 . 0 i n s t ru c t i o n s e t su mm a ry . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 5 3 0 . 0 i n - ci r cu i t s e r i a l p r o g r a m m i n g ? ( i c s p ? ) . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 5 31. 0 d evelopm ent suppor t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 2 0 7 3 2 . 0 p a c ka g i n g in fo r m a tio n . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. . 2 1 1 appendix a : revision hi s t or y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 1 7 i ndex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 2 1 9 t h e m i c r o ch i p w e b s i te . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. . .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 2 2 5 cust omer change not i f i cat i on se rvice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 2 2 5 cust omer s upport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 2 5 p r o d u ct i d e n t i f i c a t i o n s ys t e m .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 2 7 http:///
? 2014 microchip technology inc. ds20005281a-page 7 mcp191 14/5 t o our v a lue d cus t o me rs i t i s our int ent ion t o pr ovide our valued cust omer s wi t h t he bes t docum ent at ion possible t o ensu r e s u cce ssf ul us e of your m i c r o chi p product s . t o t h is end, we wi ll cont i n ue t o i m prov e our pu bl ica t ions t o bet t e r s u it your needs . o u r publicat ions w i ll be r e f i ned and enhanced as new volumes and updat es ar e int r oduced. i f y ou have any quest i on s o r c o mm ent s r egar ding t h is publicat ion, p l eas e c ont ac t t h e m a rket ing co mm uni c a t i ons dep a r t m e nt via e - m a il at d o cerro rs@mi c ro ch i p . c o m . w e w e l c ome your f e edback. mo st cu r r en t da t a s h ee t t o obt ain t he mos t up-t o -dat e ver s ion of t h is dat a s heet , please regist er at our w o rldwide w eb sit e at : h t t p : / /www . m i c r o c h i p . c om y ou can det erm i ne t he v e rsion of a dat a s heet by examining i t s li t e rat u re nu mber f ound on t he bot t o m out s i de cor ner of an y p a g e . t h e last c haract e r of t he li t e rat u re number is t he vers i on num ber , (e . g . , ds3000000 0a i s ve rsion a of docume n t ds3000000 0 ). er rat a an errat a she e t , desc r ibing minor operat ional dif f erences f r om t he dat a sheet and recom m ended workar ounds, m a y ex i s t f o r curre n t devices . a s device/ docum ent at ion issu es bec ome k nown t o us , w e will publi s h an er rat a sheet . t he errat a will spec i f y t he revisi on of silicon and rev i sion of doc ument t o whi c h it applies. t o det er mine if an errat a sheet exis t s f o r a p a rt i c ular dev i ce, please chec k w i t h one of t he f o ll o w i n g : ? m icr o chip? s w o rldwide w eb sit e ; h t t p : / /w ww . m ic r o c h ip. c om ? y our local m i croc hi p sales of f i ce (see last p age) w hen cont act i ng a s a l e s of f i c e , please s pecif y which device, re vision of sili c on and dat a s heet (inc l u d e lit erat ur e number) you are using. cu st o m er no t i f i c a t i o n sy st em register on our web site at www.microchip.com to receive the most current information on all of our products. http:///
MCP19114/5 ds20005281a-page 8 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 9 mcp191 14/5 1 . 0 d ev ic e o ver vi ew th e m c p191 1 4/5 are h i gh ly inte gra t ed, mi xed si gna l l o w - si de s y n c h r ono us c o n t rol l ers that o pera t e fro m 4 . 5v t o 4 2 v . t he f a m ily fe atu r es an an alo g pw m c ont roll er w i th a n in teg r ate d m i c r oc ontr o ll er c o re use d fo r led li ghti ng s y s t em s , bat tery c h a r ge rs an d oth e r l o w - si de sw it ch p w m a p p lic ati ons . th e d e vi ce s fe atu r e an ana lo g int e rna l pwm co ntrol l e r s i m i l a r to th e m c p16 31, and a s t an da rd pic ? m i c r oc on troll e r s i m i l a r to the pic 1 2f61 7. c o mpl ete c us t om iz ati on of d ev i c e o per atin g p a ram e t e rs , s t a r t-up o r s h u t do w n profi l e s , pro t ec tio n l e v e ls an d f aul t ha nd lin g p r oc edu res are ac co mp li she d b y set t in g d i gi t a l reg i s t ers u s i ng mi cro c h i p? s m p lab ? x i nt e gr a t ed d ev el o pm en t e n vi r o nm en t s oft w a r e a nd o ne o f mi cro c hi p? s m a n y in -ci r cu it d ebu gge r and dev ic e pr o g r am me r s . th e m c p191 1 4 /5 mi xe d s i gn al l o w - s i de sy nc hro nou s c ont roll ers fe ature in teg r ate d pr ogram m a b l e inp u t u v l o /o vl o, prog ram m abl e outp u t ov erv o lt age ( o v), tw o lo w - si de g ate dri v e out put s w i th i nde pe nde nt p r ogra m m a b l e de ad tim e , pro g ra mm abl e lea d i ng edg e b l an ki ng (fo u r st ep s ) , pro g ra mm abl e 6-b i t s l op e c om pen sa tio n a nd an inte gra t ed int erna l p r ogram m a b l e os cil l a t or f o r fi xe d-fre que nc y a ppl ic ations . an int egrat ed 8 - bit re ferenc e vol t ag e (v re f ) is us ed fo r s e tti ng out put vo lt a ge or c u rre nt. an i nter nal co mp ara t or s up port s qua si -res ona nt a ppl ic atio ns . add i tio n a l c apt ure a nd c o m p a r e m o d u le s are int egra t ed for ad di tion al c o n t rol , inc l u d in g e nha nc ed di mm in g ca p ab i l i ty . th e mc p1 91 14 /5 de v i c es c on t ai n t w o in t er n a l ld o s . a 5v ld o i s u s ed to pow e r the i n te rnal proc es so r and p r ov id e 5v e x te rnal ly . t h is 5v e x t e rna l ou tpu t ca n b e us ed to s upp ly th e ga te driv e. an a nal og fil t er b e tw e en t he v dd o u tpu t and t he v dr i npu t is re com m end ed w h e n i m p l em en tin g a 5v g a te dri v e su ppl ied fro m v dd . t w o 4 . 7 f c a p a c i tor s are rec o m m e nde d w i th one pl ace d a s c l os e a s po ss ib le to v dd a nd o ne a s c l os e a s p o ss ib le to v dr , se par a t ed by a 1 0 ? is ol ati on re si sto r . d o n o t ex cee d 10 f on th e v dd . an ext e rna l su ppl y i s req u i r ed to im ple m e n t hi ghe r gat e dri v e v o l t ag es . by u t il izi ng m i c r oc hip ? s tc 12 40a v olt a ge d oub ler s upp lie d fro m v dd to pro v i de v dr , a 10 v gat e dri v e c a n b e a c hi ev ed. a 4v ld o is us ed t o po w e r the int e rna l a nal og cir c ui try . t he tw o l ow - si de dri v ers c an be use d to ope rate t he po w e r co nv erter in bi di rect ion a l m o d e , e nab lin g the ?sh a p i ng ? of led di mm in g c u rre nt in led a ppl ic atio ns or de ve lop i ng bid i re cti ona l po w er c onv ert e rs for batt e ry -pow e r ed app lic ati o n s . th e m c p1 91 14 is p a c k ag ed i n a 24- lea d 4 m m x 4 m m qf n . t h e mc p 1 91 15 i s pac ka ge d i n a 2 8 - l e a d 5 m m x 5 mm qf n. t h e ab il i t y fo r sy st em d e si gn e r s t o co n f i g ur e ap pl ic atio n-s pec if ic f eatu r es all o w s t he m c p19 1 1 4 /5 to be o f fe red in sm al le r p a c k a g e s tha n c u rre ntl y av ail a bl e i n in tegr ated de vic e s tod a y . t he g e n e ra l purp os e in put /ou t pu t (g pio ) of th e mc p1 91 14 /5 c an b e c onf igu r ed to of fer a s t at us ou tput , a de vi ce en abl e, to c ont rol a n ex ter nal sw it ch, a s w i t c hin g fre que nc y s y n c h r oni za tion o u tpu t o r i npu t o r ev en a de vi ce st atu s or "h ear tbea t" ind i c ato r . t his f l ex ib ili ty al low s th e mc p 1 9 1 14 / 5 pac ka g e s an d c o m p l e t e so l u t i on s t o be sm al l e r , t h e r eb y sa vi n g si ze an d c o s t o f t h e sy st e m pr inte d c i rc ui t bo ards . wi th i n te grat ed fe atu r es lik e o u tpu t c u rrent ad jus t an d dy na mi c out put vo lt a ge po sit i on ing , t he mc p1 91 14 /5 fa mi ly has th e b e s t in cl as s p e rfo r ma nc e a nd hig h es t i nteg r ati on lev el cu rren t ly av ail ab l e. po w e r t r ain s su ppo rted b y thi s arc h it ect u re in cl ude b u t ar e not l i m i te d to bo os t, fly bac k , q u a s i-r e so na nt fl y b ac k , sepi c, ? uk , et c. t w o lo w - si de gate dri v e r s a r e c a p a b l e of sin k i ng and so urci ng 1a a t 10 v v dr . w i th a 5v gat e dr ive , th e d r iv er i s c ap abl e o f 0.5 a s i nk an d s ourc e . the use r ha s th e op tio n to all o w the v in uvl o to s hut dow n the dr ive r s by se tti ng the u v lo en bi t. wh en thi s bi t is n o t se t, t he devic e dri v ers w i ll rid e th roug h the u v lo c o n d it ion a nd co nti nue to op era t e un til v dr reac he s the gate dri v e u v lo v a lu e. thi s v a lu e i s s e l e c t abl e a t 2. 7v or 5.4 v and is al w a y s en ab led . an inte rna l re set for the mi cro c on trolle r co re i s s e t to 2.0 v . an in ternal co mp arat or m o d u le i s use d to s ens e th e de sa turat i on of th e fly b a c k trans fo rme r to s y n c h r oni ze s w itch in g for qu as i-re son a n t a ppl ic ati o ns . th e o pera t in g i npu t vo lt a ge for n o rm al devic e o p era t io n ra nge s from 4 . 5v to 42v w i th an a b s o lu te ma xi mum of 44 v . the m a x i m u m t r ans ie nt vo lt a ge i s 48v fo r 5 0 0 m s . an i 2 c seri al bus is us ed for d e v i c e c o m m u n ic ati o n s fro m the pwm co ntro lle r to the sy st em. http:///
MCP19114/5 ds20005281a-page 10 ? 2014 microchip technology inc. figure 1-1: mcp 191 1 4 /5 fly back s y nchrono us quasi - re sona nt block diagra m v dd (5v) bgap uvlo v ref ov ref 8 8 ov bgap pic core osc ov uvlo pdrv i sn a=10 i p leb 2 ea_sc pwm comp pwm logic desat n qrs v dr a gnd mclr dimi sda temp v s bin i/o x 3 (x7 mcp19115) ov oc clamp 6 ccd 4 4 en1 en2 ovlo 4 i fb p gnd p gnd p gnd v vdd v ref2 mux to gpb1 i/o ldo1 ldo2 bias gen av dd (4v) v avdd v dd v ref2 8 desat mux 4v to 20v 8.8v to 44v en bgap desat p /i sout i sp v dd_ok rfb mux bg 5k gate drive timing gate drive timing i p_comp a2 a1 ov_ref v ref2 v ref a2 ovlo_ref uvlo_ref l in interrupt and logic to pwm & pic l in l in r fb_int amux 5v to 10v 4m s b vin_uvlo log lin slope comp adj offset vin_ovlo + - - + ovlo dmux pwm vzc vzc vzc vzc v dr uvlo bgap 2.7v or 5.4v adc 4m s b 2lsb 2lsb bgap bgap chs1 chs2 chs3 chs4 chs5 chs6 chs8 chs9 chs10 see electrical characteristics for clamp voltages v in pdrv i p sdrv desat n desat p i sn i sp gpio gpio a gnd p gnd v vdd v vdd v vdd v dr i comp 4.5v to 42v 4.7 f 4.7 f 10 place recommended v vdd and v dr 4.7 f capacitors as close to respective pins as possible chs0 v in/n http:///
? 2014 microchip technology inc. ds20005281a-page 11 mcp191 14/5 figure 1-2: mcp 1 9 1 1 4 cuk? sy nchronous p o s i tiv e outp ut ap plicati o n diagram figure 1-3: MCP19114 boost quas i-resonant application diagram v in v dr i sp p gnd v s i p v in pdrv bin dimi desat n mclr ccd MCP19114 i comp i/o temp sns en 2 sdrv a gnd v dd i fb 4x424ldqfn v dd i/o i/o i/o 2 v dd 5v desat p i sn i/o tc1240 voltage doubler 10v v in v dr i sp p gnd v s i p v in pdrv bin dimi desat n mclr ccd MCP19114 i sn i comp i/o temp sns en a gnd v dd i sout i fb 4x424ldqfn v dd i/o v dd 5v 2 sw1 sw2 desat n desat n desat p desat p desat p sdrv sw1 sw2 i/o i/o 2 http:///
MCP19114/5 ds20005281a-page 12 ? 2014 microchip technology inc. figure 1-4: micr o c o ntr o lle r core block diagram fl a s h progr am m e mory 13 data bus 8 14 progra m bus i n st ruct i on reg pr ogram count er ra m f ile regist ers direct a ddr 7 ra m a d dr 9 a ddr m u x i ndirec t ad d r fs r r e g st a t u s r e g mu x alu w re g i n st r u ct i o n de code & cont rol ti m i n g g enerat i o n te stc l k i n po r t gp a 8 8 8 3 8 l e v e l s t ack 25 6 4k x 14 by t es (13-bit ) p o wer-up ti m e r p o wer-on r e set w atchdog timer mclr v in v ss t i mer0 timer1 t0 cki conf i gur at ion 8 m hz i n te r n a l o s cil l at or ti mer2 i 2 c gpa 0 gp a 1 gp a 2 gp a 3 gp a 5 ana l og i n t e rf ace sd a scl pmd a t l e ead d r self read/ writ e f l as h mem o ry r egisters port gpb gp b0 gp b1 gp b6 ( mcp19115 ) gpb4 ( mc p 1 9 1 1 5 ) pwm gp b5 ( mcp 1 91 15 ) gpa 6 gp a 7 gp b7 ( mcp19115 ) enhan ce d ccd gp a6 gpb7 (mcp19115) http:///
? 2014 microchip technology inc. ds20005281a-page 13 mcp191 14/5 2.0 p in de s cript i o n th e 24-l ead m c p191 1 4 a nd 28-l e a d m c p19 1 1 5 devi c e s fe atu r e pi ns that h av e m ult ipl e fun c t i on s asso c i ate d w i th ea ch pi n. ta b l e 2 - 1 pr o v i d es a d e sc rip t io n o f th e dif f ere n t fun c ti ons . re fer to se ction 2 .1 ? d et a ile d pi n func tiona l desc r i ption? fo r m o re det a i l ed i n fo rma t io n. t able 2 - 1 : mcp 191 1 4 /5 p i nout de s crip t i o n nam e func tion inp u t ty p e ou tp u t ty p e d esc r i ptio n gp a0/an0/ t est_ o ut g p a0 tt l c m o s g e nera l -pu r po s e i/o an 0 a n ? a / d c han ne l 0 inp u t test _o u t ? ? i n te rnal an alo g /d igi t al si gna l m u l t ip lex e r o u tp ut ( 1 ) gp a1 / a n1 / c l kpi n g p a 1 t t l cm os gen e r al -p urp o s e i / o an 1 a n ? a / d c han ne l 1 inp u t c l kpin s t c mo s s w i tc hin g fre que nc y c l o c k in put or o u tp ut ( 2 ) gp a2/an2/ t 0cki/ i nt g p a2 st cm os ge nera l -pu r po s e i/o an 2 a n ? a / d c han ne l 2 inp u t t 0 ck i s t ? t i m e r 0 cl oc k i n p u t int s t ? e x te rnal in terru pt g p a3/an3 g p a3 tt l c mo s g e nera l -pu r po se i/o an 3 a n ? a / d c han ne l 3 inp u t gp a5 / m cl r gpa5 ttl ? general-purpose input only mclr st ? master clear with internal pull-up gpa6/ccd/icspdat gp a 6 st cmos g e nera l -pu r po se i/o icspda t st cmo s s e ria l pro g ram m i ng dat a i/o c c d s t c mo s s ing l e c o mp are out put . d ua l c ap t ure in put g p a7/sc l /ic spc lk gp a7 st od g e nera l -pu r po se ope n d r ain i/o scl i 2 c? o d i 2 c cl o c k icspclk st ? s eria l pro g ram m i ng clo c k gpb0/ s da gpb0 tt l o d g e nera l -pu r po s e i/o sd a i 2 c? o d i 2 c d a t a input/output gpb1/ a n4/vref2 gpb1 tt l c m o s g e nera l -pu r po s e i/o an 4 a n ? a / d c han ne l 4 inp u t vref2 ? an v r ef 2 dac out put ( 3 ) gpb4/ a n5/icspda t ( mcp 19115 only) gpb4 ttl cmos g e nera l -pu r po se i/o an 5 a n ? a / d c han ne l 5 inp u t icspda t st cm os p rimary serial programming data i/o gpb5/an6/icspclk ( mcp1 91 1 5 on l y ) gp b 5 t t l c m o s g en e r al - p ur p o s e i / o an 6 a n ? a / d c han ne l 6 inp u t isc p c l k s t ? p r im ary seri al pr ogra m m i n g cl o c k le ge n d : an = a nalog input or out put c m o s = c m o s c o mp at ible input or out put o d = o pen drain t t l = t t l c o mp at ible input s t = s c h mit t t r igger input wit h cmo s levels i 2 c = s chm it t t r i gger input wit h i 2 c note 1 : t he a nal o g / digit al debug o u t put is select ed t h rough t h e cont rol of t he ab eco n regist er . 2: select ed w hen f unct i on i ng as mas t er or s l ave by prope r co nf igurat ion of t he m s c<1: 0> bit s in t he mo dec o n regist er . 3: vre f 2 out put select ed when c onf igured as mas t er by proper conf igurat i on of t he m s c<1: 0> bit s in t he mo de co n regist er . http:///
MCP19114/5 ds20005281a-page 14 ? 2014 microchip technology inc. gpb6/ a n7 ( mcp 1 91 1 5 on l y ) gp b 6 t t l c m o s g en e r al - p ur p o s e i / o an 7 a n ? a / d c han ne l 7 inp u t gpb7/ c c d ( mcp 1 91 1 5 on l y ) gp b 7 t t l c m o s g en e r al - p ur p o s e i / o c c d s t c mo s s ing l e c o mp are out put . d ua l c ap t ure in put. v in v in ? ? d e vi ce in put sup p l y v o l t ag e v dd v dd ? ? internal +5v ldo output pin v dr v dr ? ? g a te d r iv e s upp ly vo lt a g e a gn d a gn d ? ? s m al l s i g nal qu iet gro und p gn d p gn d ? ? l a rg e s i gn al pow e r gro und pdr v pdr v ? ? p r im ary low-si d e m o sfet ga te d r iv e sd rv sdrv ? ? secondary low-side mosfet gate drive i p i p ? ? p r im ary inp ut curr ent se nse i sn i sn ? ? s eco nd ary cu rrent se ns e am pl ifi er n ega tiv e i npu t i sp i sp ? ? s eco nd ary cu rrent se ns e am pl ifi er p os i tiv e inp ut v s v s ? ? s ens e v o l t ag e c o m p are d to ov erv o l t ag e d a c i fb i fb ? ? e rror a m p lifi e r f eed bac k inp u t i co m p i co m p ? ? e rror a m p lifi e r o u tp ut desa t p /i so u t desa t p /i so u t ? ? desa t p : d esa t det ec t co mp ara t or p o s i ti ve inp u t i so u t : sec o n dary c u rre nt s ens e am pli f ie r out put desa t n desa t n ? ? desa t n : d esa t d e te ct co mp arato r ne gat i v e in pu t t a ble 2 - 1 : mcp 191 1 4 /5 p i nout de s crip t i o n ( c o n ti nued) nam e func tion inp u t ty p e ou tp u t ty p e d esc r i ptio n le ge n d : an = a nalog input or out put c m o s = c m o s c o mp at ible input or out put o d = o pen drain t t l = t t l c o mp at ible input s t = s c h mit t t r igger input wit h cmo s levels i 2 c = s chm it t t r i gger input wit h i 2 c note 1 : t h e a nal og / digit al debug o u t put is select ed t h rough t h e cont rol of t he ab eco n regist er . 2: select ed w hen f unct i on i ng as mas t er or s l a ve by prope r co nf igurat ion of t he m s c<1: 0> bit s in t he mo dec o n regist er . 3: vre f 2 out put select ed w hen c onf igured as mas t er by proper conf igurat i on of t he m s c<1: 0> bit s in t he mo de co n regist er . http:///
? 2014 microchip technology inc. ds20005281a-page 15 mcp191 14/5 2. 1 d et ai le d pi n func ti onal descr ipt i on 2.1 . 1 g p a 0 p i n g p a0 is a gen eral -pu r pos e tt l inp u t or c m o s o u tp ut p i n w h os e da t a d i re cti on i s con t rol l ed in tr isg p a. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 0 is an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 0 , b i t s tr isa0 a nd an sa0 mu st b e se t . th e abecon regi s te r c a n be c o n fig ured t o s e t thi s pi n to t he test_ o u t f unc tio n . it is a b u f f ere d out put of th e i n ter nal an al og or dig i t a l s i g nal m u l t ipl e x e rs . an alo g s i g nal s pre s e n t on this pi n are c o n t rol l ed by th e ad c o n 0 reg i s t er . d i git a l s i g nal s pre s e n t o n thi s pi n a r e c ont roll ed by the abecon regi s t er . 2.1 . 2 g p a 1 p i n g p a1 is a gen eral-pu r pos e tt l inp u t or c m o s o u tp ut p i n w h os e da t a d i re cti on i s con t rol l ed in tr isg p a. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 1 is an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 1 , b i t s tr isa1 a nd an sa1 mu st b e se t . when th e mc p1 91 14 /5 are confi g u r ed as a m aster o r sl a v e , this pi n is c o n f ig ured to be t he s w itch in g fre q u enc y sy nc hroniz ation i npu t o r out put (c lkpin ) . 2.1 . 3 g p a 2 p i n g p a2 is a gen eral -pu r pos e st inp u t o r c m o s o u tp ut p i n w h os e da t a d i re cti on i s con t rol l ed in tr isg p a. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 2 is an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 2 , b i t s tr isa2 a nd an sa2 mu st b e se t . w hen b i t t0cs is se t i n the o p ti o n _ r eg reg i s t er , th e t0 c k i fun c ti on i s en abl ed. r e fer to se ction 2 2 . 0 ? t i m er 0 mo dule? fo r m o re inf o rm atio n. g p a2 can a l s o be c onfi gur ed as a n ex ternal in terru pt b y se ttin g the inte bit . re fer to se ction 1 4 . 2 ? g p a 2/ int int e rrupt ? for mo re i n for m a t ion . 2.1 . 4 g p a 3 p i n g p a3 is a gen eral-pu r pos e tt l inp u t or c m o s o u tp ut p i n w h os e da t a d i re cti on i s con t rol l ed in tr isg p a. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 3 is an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 3 , b i t s tr isa3 a nd an sa3 mu st b e se t . 2.1 . 5 g p a 5 p i n g p a5 is a g ene ral-p u rp os e tt l in put onl y p i n. an i n tern al w eak pu ll -up and in terru pt-o n-ch an ge a r e a l s o av ai la ble . f or pr o g r am mi ng p u r po se s , th i s pi n i s to be c on n ec t ed to the mcl r p i n of th e s e ria l pr ogra mmer. refer to section 30.0 ?in-circuit serial programming? (icsp?)? for more information. this pin is mclr when the mclre b i t i s s e t i n th e config re g i ste r . 2.1 . 6 g p a 6 p i n g p a6 is a ge nera l -purpo se c m o s o u tp ut st in pu t pi n w h os e d a ta di r e ct io n is c o nt r o ll ed i n t r i s gp a . ic spd a t i s a ser i al prog ram m i n g dat a i/o fu nc tio n . th is ca n b e u s e d i n c onj unc ti on w i th ic spc lk to s e ria l pr ogra m t he dev ic e. gp a6 is p a rt o f the c cd m odu le . for m o re i n fo rm a t io n, re fer t o se c t io n 2 6 . 0 ? d ua l ca p t ure / co m p a r e (ccd) m odul e? . 2.1 . 7 g p a 7 p i n g p a7 is a tr ue op en dr ain g ene ral-p u rp os e pin w h os e da t a d i rec t io n is c o n t rol l ed in tr isg p a. the r e is n o i ntern al co nne ct ion be tw een th is pi n a nd dev ic e v dd . th is pi n d oes n o t hav e a w e a k pul l-u p , b u t int e r- ru pt-o n-ch an ge i s ava i l abl e. th is pin is t he pr im ary i c s p c l k inp u t. f o r m c p191 1 5 , th is pin is al t1 _ic spc lk. thi s c a n be use d i n c onj unc ti on with icspda t to se ria l p r og ram th e de vi ce . wh en th e m c p 191 14 /5 i s co nfi gured for i 2 c co mm un i c a t io n, se ction 2 8 . 2 ?i 2 c mo de ov er v i ew ? , g p a7 fu nct i on s a s t he i 2 c cl oc k ( s cl ) . t h i s pi n mu st be c onfi g u r ed as an i n p u t to al low proper o perat io n. http:///
MCP19114/5 ds20005281a-page 16 ? 2014 microchip technology inc. 2.1 . 8 g pb 0 p i n g pb0 is a tru e o pen dr ain ge ner al-p urpo se pi n w hose d a t a di rec t io n i s co ntro lle d i n tr isg pb. t here is n o i nter nal co nn ect i on be tw ee n th is pi n a nd dev ic e v dd . th is p i n do es no t hav e a w eak p u ll -up , b u t i n ter r upt -on-c h a nge is a v a ila bl e. wh en th e m c p19 1 1 4 /5 are c onf igu r ed f o r i 2 c co mm uni ca tio n , se ction 2 8 . 2 ?i 2 c mo d e ov er v i ew ? , g pb0 fun c t i on s a s t he i 2 c c l oc k ( s d a ) . t h is pi n m us t b e c on f ig u r ed as a n in pu t to all o w p r ope r op erat ion . 2.1 . 9 g pb 1 p i n g pb1 is a ge ne ral-p u rp ose t t l inp u t or c m o s o u tp ut p i n w h o s e d a t a dire cti on i s c ontro ll ed in tr isg pb. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 4 i s an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 4 , b i t s tr isb1 a nd an sb1 mu st b e se t . w hen th e mc p1 91 14/ 5 are c o nfi gure d as a m aster , th is pi n i s c onf igu r ed to b e th e v re f 2 da c outp u t. 2.1 .10 g p b 4 p in ( m cp 19 1 1 5 o n l y ) g pb4 is a ge ne ral-p u rp ose t t l inp u t or c m o s o u tp ut p i n w h o s e d a t a dire cti on i s c ontro ll ed in tr isg pb. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 5 i s an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 5 , b i t s tr isb4 a nd an sb4 mu st b e se t . ic spd a t i s the prim ary s e ri al p r og ram m i ng dat a i/o fu nc tio n . t h is i s u s e d i n c o n j un cti on with icspclk to s e ri al p r og ram the de vi ce. 2 . 1. 1 1 gp b5 pi n ( m cp 19 1 1 5 o n l y ) g pb5 is a ge ne ral-p u rp ose t t l inp u t or c m o s o u tp ut p i n w h o s e d a t a dire cti on i s c ontro ll ed in tr isg pb. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 6 i s an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 6 , b i t s tr isb5 a nd an sb5 mu st b e se t . ic spc l k is th e pri m a r y ser i al pro g ramm i ng cl oc k fu nc tio n . th is is us ed in c o n j un cti o n with icspda t to s e ri al p r og ram the de vi ce. 2.1 .12 g p b 6 p in ( m cp 19 1 1 5 o n l y ) g pb6 is a ge ne ral-p u rp ose t t l inp u t or c m o s o u tp ut p i n w h o s e d a t a dire cti on i s c ontro ll ed in tr isg pb. an i n ter nal w eak p u ll -up and in terru pt-o n-c han ge are als o a v ai la ble . an 7 i s an in put to th e a/d . t o c onf igu r e thi s pin t o b e re ad by th e a/ d on c han nel 7 , b i t s tr isb6 a nd an sb6 mu st b e se t . 2.1 .13 g p b 7 p in ( m c p 19 1 1 5 o n l y ) g pb7 is a ge ner al-p urpo se tt l inp u t or c m o s o u tp ut pi n w h o s e d a t a d i re cti on i s contro lle d in tr isg pb. an i n tern al w eak pu ll -up and in terru pt-o n-ch an ge a r e a l s o av ai la ble. gpb7 i s p a rt o f th e ccd mo d u l e . f o r mo r e i n fo rm a t i o n , re fer t o se c t io n 2 6 . 0 ? d ua l ca p t ure / co m p a r e (ccd) m odul e? . 2.1 . 14 de sa t n pin in ternal co mp arat or i n v e rti ng inp u t. u s e d d u rin g qu as i-re so nan t op erat ion for desatu r ati on det ect i on . 2.1 . 15 de sa t p /i so u t pi n wh en u s i ng t he i n tern al com p a r ato r for d e sa tura tio n de tect io n duri ng qu asi -res o n ant op erati o n , th is pi n c onn ec t s t o the co mp arat or ? s n on- inv erti ng i npu t. th e ou tpu t of t he re mo te s e n s e c u rre nt s e n s e am pli f ie r get s c onf igu r ed t o ut ili ze the 5 k ? in ter n a l fe edb ac k r e si sto r . w he n no t ut i l i z i n g t h e in t er n al c om p a r at o r a nd no t co n f i g ur e d t o us e t h e 5 k ? i n te r n a l fe edb ac k r e si sto r , th e c u rre nt s ense a m p l i f ier get s c onn ec ted to t h is pi n an d i s i so u t . 2.1 . 16 i sp pi n th e n on-i n v e rti ng inp u t t o i n ternal cu rrent se ns e am pl ifi er , typic al l y us ed to dif f ere nti all y rem ote se ns e s e c ond ary cur r ent. thi s pi n c an b e in ternall y pu ll ed-up to v dd b y s e ttin g t he bi t i n the pe1 reg i s t er . 2.1 . 17 i sn pin th e inv e rt ing i npu t t o inte rna l c u rr ent s ens e am pli f ie r , ty pi ca lly us ed t o di f f e r ent ial l y rem ote s en s e sec on dar y c u rre nt. 2.1 . 18 i p pin pri m a r y inp u t cu rrent se ns e f o r c u rre nt mo de co ntro l an d p eak cu rren t li mi t. fo r vo lt a ge m od e c ont rol, thi s pi n c a n be co nne cte d t o an art i fic i a l ra mp . 2.1 . 19 a gnd pin a gn d i s th e s m a l l si gna l g r oun d c onn ec tio n p i n. thi s pi n s hou ld b e co nne cte d to th e ex po se d p ad on th e bo tto m o f th e p ack ag e. 2.1 . 20 p gnd pi n c o n nect all la rge si gna l l e v e l grou nd retu rns to p gn d . th es e la rge- sig n a l le ve l gro und trac es sh oul d ha ve a s m a ll lo op are a and m i ni ma l len gth to p r ev ent c oup lin g of sw i t ch in g no is e to se ns iti v e trac es . http:///
? 2014 microchip technology inc. ds20005281a-page 17 mcp191 14/5 2.1 . 21 sdr v pi n th e ga te of t he lo w - si de s e c ond ary mo sfet i s c onn ec ted to s d r v . th e pc b tr ace co nn ect i ng sd r v to th e ga te mu st be o f m i n i m a l l e n g th and ap prop ria t e w i d t h to han dle the h i gh p eak dri v e c u rre nt an d fas t v o l t age tra n si tio n s . 2.1 . 22 pdr v pi n th e g a te of th e l o w - s i de pri m ar y m o sfet i s c onn ec ted t o pd r v . the pc b t r aci n g c o n nec tin g pd r v to th e g a te mu st b e o f mi ni ma l le ngt h an d a ppro p ria t e w i d t h to han dl e th e h i gh-p e a k d r iv e c u rre nt s an d fa st vo lt ag e t r ans iti ons . 2.1 . 23 v dr pin th e su ppl y for the lo w - si de dri v er s i s co nne ct ed to thi s p i n and h a s an a b so lu te m a x i m u m ra tin g of +13 . 5v . th is pi n c a n be co nne ct ed by an r c fil t er to t he v dd pi n . 2.1 . 24 v dd pin th e o u tp ut of t he inte rna l + 5 .0v reg u la tor is co nne cte d t o th i s pi n. it is r e co mm en de d t h at a 1 . 0 f by p a ss c a p a ci tor be co nne cte d betw e en thi s pin an d t he gn d p i n of the de vi ce . t he by p a s s c a p a c i t or sh oul d b e ph y s i c a l l y p l a c ed cl os e t o th e de vi ce . 2.1 . 25 v in pi n in put p ow er co nne cti on pi n of the de vi ce . i t i s rec om m e n de d t h at c apac i t a n c e be pl a c e d b e t w e e n t h is p i n a nd the g n d pin of the dev ic e. 2.1 . 26 v s pi n an alo g inp u t c onn ec ted to t he no n-inve rting inp u t of th e o v erv o l t ag e com p arato r . t y pic a l l y us ed as o u tp ut v o l t age ov ervolt a g e p r ote c ti on . the i n v e rti ng i npu t of th e ov ervolt age c o m p ar ator is con t rol l ed b y the o v ref dac. 2.1 . 27 i fb pi n error am pl ifi e r i n ve rting f eed bac k con n e c ti on. 2.1 . 28 i comp pi n erro r ampl ifi e r o u tpu t s i gn al . 2.1 . 29 ex po s e d pa d ( e p ) it is rec o m m e nde d to co nne ct t he e x p o s ed p a d to a gn d . http:///
MCP19114/5 ds20005281a-page 18 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 19 mcp191 14/5 3.0 f unctional de s cription 3. 1 l i n ear regul ator s th e ope rati ng in put v o lt age fo r th e mc p1 91 14 /5 ra nge s fro m 4.5 v to 42 v . ther e are tw o i n te rnal low d r o pou t (ld o ) v o lt age reg u la tors . a 5 v ld o is us ed to p o w e r the int e rna l p r oc es so r an d p r ov ide a 5v o u tp ut fo r ex ter nal us age . a s e c o n d ld o (v av d d ) is a 4v re gul ato r an d is us ed to p o w e r the rem a in in g an alo g i nter nal ci rcu i try . u s i ng a n l d o t o po w er th e mcp191 1 4 /5 , the i npu t v o l t ag e is m o n i to red us in g a re si sto r di vid er . the mc p1 91 14/ 5 al so in corp ora t e brow n-o u t prot ect i on . r e f e r t o se ction 1 3 . 3 ? b rown-out rese t (bor)? for de t a il s. th e pi c co re w i ll r ese t at 2.0 v v dd . 3. 2 o ut put dri ve ci rcui tr y th e mc p1 91 14 /5 in teg r ate t w o l o w - s i de driv ers use d to d r iv e the e x te rnal l o w - s i de n - c h ann el po w e r m o sfet s f o r s y n c h r ono us ap pli c a t io ns , s u c h a s sy nc hr o n o u s f l yb ac k a n d sy nc h r on ou s ? uk co nve r ters . bo th con v e r ter typ e s c an be co nfi gured for n on-s y n c h r ono us co ntro l b y re pl aci n g the sy nc hro nou s fe t w i th a dio de . th e fl yb ac k i s als o cap ab l e of q uasi-re so nan t o pera t io n. the m c p191 1 4 /5 ca n als o b e c o n f ig ured a s a boo s t or sepic s w i t c h -m o d e po wer s upp ly (sm ps). in boo s t mo de, non -sy n c h ro nou s fi xe d-fre que nc y or non -sy n c h ron o u s qua si -res ona nt c ont rol ca n b e u t il iz ed. thi s dev ic e ca n a l s o b e u s e d a s a sepi c sm ps in fi x e d - freq uen c y non -s y n c h ro nou s m o d e . the lo w - si de dri v e is c a p abl e of sw i t ch ing th e m o sfet a t h i gh fre que nc y i n t y pi ca l sm ps a ppl ic atio ns . th e ga te d r iv e (v dr ) ca n be su ppl ie d fro m 5 v t o 10v . th e dri v e s t re ngth is c a p abl e of up t o 1a s i n k /s our ce w i th 10v gat e dr ive an d d ow n t o 0 . 5a s i n k /s our ce w i t h 5v ga te dri v e . a p r ogra m m a b l e d e la y i s u s e d to s e t t he gate tu rn-on de ad tim e . thi s p r ev ent s o v er lap and sh oot-t hrou gh c u rre nt s tha t c an d e cr ease th e co nve r ter ef fici e n c y . ea ch dri v e r s h a ll hav e it s ow n en i npu t c ont rolled by the mi cro c o n tro lle r c o re. 3. 3 c urrent sense th e out put c u rre nt is d i f f e ren t ia lly se nse d by th e m c p19 1 1 4 /5 . in low - c u rre nt app lic ati o n s , t h is he lp s m a i n t a in h i gh sy st em ef f i c i en cy by mi nim i z i n g po w e r d i s s ip ati on i n cu rren t se nse res i s t ors . d i f f ere n tia l c u rre nt s e n s i ng a l s o m i n i m i z e s ex terna l g r ou nd s h i f t e rrors . the inte rna l di f f e r ent ial am pli f ie r h a s a pre c i s io n g a in of 10v/v . 3. 4 p eak curr ent mode th e m c p19 1 14/5 is a pe ak cu rrent mo de co ntro lle d de vi ce w i th th e c u rre nt sen s i ng ele m e n t in se ries w i th th e prim ary si de m o sf et . prog ram m a b l e lea din g ed ge bl ank in g c an b e i m p l em en ted to bl an k c u rre nt s p ik es res u lti n g fr om tu rn on . the b l an k tim e i s c ont roll ed from th e ic l ebc on re gi ste r . pri m a r y in put c u rren t of fs et ad jus t is al so a v a ila ble vi a us er p r ogram m a b ili ty , th us l i m i tin g pe ak p r im ary i n p u t c u rre nt. th is of f s e t adj us tme n t i s c ont rolled b y th e icoacon re g i s t e r . 3. 5 m agnet i c desat urat ion detec t i o n an i n te rnal co mp arat or m o du le i s us ed to de tect po w e r tra i n ma gne tic de sat u rat i on for q u a s i-r e so na nt ap pl ic atio ns . the co mp ara t or ou tpu t is us ed a s a si gna l t o syn c h r o ni ze t h e sta r t of t h e ne xt s w it c h i n g c y c l e . th is ope rati on d i f f ers from the trad iti o na l fi xe d-fre que nc y app lic ati on . th e d e s a t co mp arat or ou tpu t ca n be en abl ed a nd ro ute d in to th e pwm c i rc uit r y or d i s abl ed fo r fix ed-frequ enc y a p pl ic ati o ns . d u ri ng qu as i-r e s o n ant (qr ) o pera t io n, th e d esa t c om p ara t or o utp ut is ena ble d an d co mb ine d w i th a p a i r of one -sh o t ti me rs a nd a f lip -flo p to s u s t ai n pwm op era t io n. t i me r2 (t mr 2) mu st be ini t ia liz ed an d s e t to ru n a t a frequ en cy lo w er th an the mi ni mu m q r op era t in g f r equ enc y . whe n the c d s wd e bi t i s se t i n th e d esa tc o n re gis t e r , t m r 2 s e rve s as a w a tc hd og. an e x a m p l e of th e ord e r of ev en t s fo r a fly b ac k sm ps in sy nc h r on ou s q r op er a t i o n is as f o l lo w s: th e pri m a r y gat e driv e (pd r v) go es h i gh . the o u tp ut of the d esa t co mp arato r is hi gh. the prim ar y c u rre nt in c r ea se s u n t i l i p reac he s th e le ve l of the e rror am p an d c aus es pwm c o m p a r ato r out put to go l o w . th e pd r v go es l o w a nd th e sec o n dary gate d r iv e (sd r v) go es high (af t e r pro g ramm e d dea d time ). th is trig ger s th e firs t on e-s hot t o se nd a 2 0 0 n s p u l s e t hat re se t s th e fl ip-f lop a nd tm r2 (wdm _reset). t h e 20 0 n s on e-s h o t pul se des ig n is im pl em ent ed to ma sk ou t an y s puri o u s tra n s i ti ons at the d esa t co mp ara t or o u tp ut c aus ed by sw i t ch ing no is e. th e sd r v st a y s hi gh u nti l th e s e co nd ary w i ndi ng com p l e te ly runs ou t of e nerg y , at w h ic h tim e the o utpu t ca p ac i t a nc e beg ins to so urc e c u rre nt bac k th roug h the w i n d i ng an d sec o n dar y m o s f et . t he d esa t c o mp ara t or d e tec t s thi s an d it s ou tpu t go es l ow . t his se t s t he f lip -flo p an d tri gge rs th e s e c ond o ne-s h o t to s e n d a 3 3 n s pu lse t o t he co ntro l lo g i c , c au s in g t h e s d r v t o go lo w an d t h e p d r v t o go hi gh (a f t er p r ogra m m e d d e a d tim e ). th e cy cl e the n re pea t s . i f, for a n y re as on, th e res e t o ne-s h o t doe s n o t fi re, the wdm _ reset s i gn al s t ay s lo w an d tm r2 i s al lo w ed t o ru n u ntil th e pwm s i g nal ki ck s of f a n ew cy cl e. th e d e s a tu rati on co mp arat or m o d u le i s c o n t rol l ed b y th e d esa tc o n reg i st er . http:///
MCP19114/5 ds20005281a-page 20 ? 2014 microchip technology inc. 3. 6 s t a rt -up t o c ontr o l th e ou tput cur r ent d u rin g s t art-u p , th e mc p 1 91 14 / 5 h a v e t h e c apab i l i t y t o mo n o t o ni ca l l y i n c r ease s y s t em cu rren t, at t he u s e r ? s di sc reti on . thi s i s a c c o m p l i sh ed thro ugh th e c ont rol of t he refer ence vo l t a g e dac (v re f ). the en tire st art-u p p r ofi l e is und er u s er co ntro l v i a so f t w a re . 3. 7 d ri ver cont rol ci rcui tr y th e int e rna l driv er co ntrol ci rcu i try o f th e mc p1 91 14 /5 i s c o m p ri sed of an e rror amp l i f ier (ea), a hig h -s pee d c o m p a r ator and a l a tc h s i m i l a r t o th e m c p163 1. th e error am pl ifier g ene rates the co ntrol vol t ag e use d b y th e hi gh -spe ed pwm com p a r ato r . th ere is a n i n ter nal ly gen era t ed referenc e v o l t ag e, v re f . th e d i f f e ren c e or erro r be tw een th is in tern al refer enc e v ol t age a nd th e a c t ual fe edb ac k vo lt a ge is t he co ntro l v ol t age . som e a ppl ic atio ns w ill im ple m e nt p a r ke d t i m es w h er e t h e ga t e dr i v e s ar e n o t ac t i v e. f o r e x am pl e, w h en ch ang ing be tw een led s t ri ngs an d a f ter v o lt age repo si tio n in g, the us er ca n dis a b l e th e g a te driv es an d p a rk the erro r am pl ifi e r o u tpu t l o w . d u ring t he ti me w h en th e ea is p a rk ed, i t s ou tpu t w ill b e c la m pe d lo w ( 1 * b g ) su ch t hat i t is i n a k now n s t a t e w h en re ac tiv a te d. be fore the out put s w itc h e s a r e re -ena bl ed, it m a y b e nec es sa ry to re -ena bl e the ea s o m e ti me p r io r to en abl in g the outp u t d r iv ers. thi s p r ior-e a ena ble ti me w ill all o w th e ea t o s l ew t o w a rd s th e inte nd ed t a rg et and p r ev ent the s e c ond ary s w itc h fro m tu rnin g on f o r an e x te ns ive peri od o f t i m e , u n in ten t ion a l l y dis c harg i ng th e o u tp ut c a p a c i t a nce an d p ull ing the ou tpu t vo lt a ge do w n. ext erna l c om pen sa tio n i s u s e d to st abi liz e t he con t rol s y s t em . si nc e the m c p191 1 4 /5 a r e pea k cu rren t m o d e c ont roll ed , th e co mp arat or c o m p a r es th e prim ary pea k c u rre nt w a v e form (i p ) th at i s ba sed u pon the c u rre nt fl ow in g in th e prim ary sid e w i th th e error am pl ifi e r c ont rol out put vo lt a ge. thi s error am pli f ie r co ntrol o u tpu t vo lt a ge a l s o has us er-pr ogra m m a b l e s l op e c o m pen sa tio n su btra cte d from it. in fi xe d-fre que nc y a ppl ic ati ons , th e sl op e c o m pen sat i on si gna l i s g ene rate d to b e gre a te r tha n 1/2 t h e do w n sl ope of th e i ndu cto r curr ent w a v e f o rm a nd is co ntrol l e d by th e sl pc r c o n reg i s t er . of fs et ad just a b il ity is als o a v ai la ble to s e t the pe ak cu rren t l i m i t of t he pri m a r y s w itc h for o v er curr ent pr otec ti on. th e ran ge of th e s l o pe co mp ens at ion ra mp i s sp ec ifi ed. w hen th e c u rre nt s ense s i g nal rea c he s t he l e v e l o f th e co ntro l v o l t age mi nus slo p e c o m p e n sa tio n , th e on c y c l e i s te rmi n a t ed an d the ex tern al s w i t c h i s la tch ed of f unti l th e be gin nin g of th e ne xt c y c l e w h ich beg ins at th e nex t cl oc k c y c l e . t o i m p r ov e c u rre nt regu lat i on at low lev e l s , a p ede st a l v o l t age (vz c ) s e t to the bg (1 .23 v ) i s im ple m e n te d. th is v i rt ual g r oun d se rve s as the re feren c e f o r the e rror a m p lifi e r (a1 ) , sl ope c o m p e n s a ti on, c u rre nt s ens e a m p lifi e r ( a 2) an d t he i p o f f s et ad j u s t me nt . an s-r la tch (se t -r es t-fl ip-f lop ) i s us ed to p r ev ent th e pwm c i rc ui try from t u rni ng the ex te rnal s w itc h o n u n ti l th e b egi nni ng of t he n e x t c l oc k cy cl e. 3. 8 f i xed p w m fr equency th e s w itc h in g fre que nc y of the m c p19 1 14/ 5 w h il e n o t c ont roll ed b y t he d esa t c o m p ara t or o u tp ut i s ge ne rate d by u s i ng a sin g l e edg e of t he 8 m h z int e rna l cl o ck. t h e u s e r se ts t h e m c p 1 9 1 1 4 / 5 swi t ch i n g fre que nc y by c o n f ig uring the pr 2 reg i s t er . th e ma xi mu m a l lo w a bl e p d r v d u t y c y c l e is ad j u s t ab le a n d i s c ont roll ed b y t he pw mr l regi ste r . th e pr ogra m m ab l e ran ge o f t he s w itc hin g freq uen cy w ill b e 31 .25 k h z to 2 m h z . t he a v a ila ble sw i t ch in g fre que nc y be lo w 2 m h z is de fin ed as f sw = 8 m h z/n, w h e r e n i s a w h o l e nu mb er be t w ee n 4 ? n ? 25 6. r e fe r to se ction 2 5 . 0 ? e nha nce d pwm m odul e? for d e t a il s. 3. 9 v ref th is re fere nce i s us ed to ge ne rate th e v o l t ag e c onn ec ted to th e n on-i n v e rti ng in put of the e rror am pl ifi e r . the e n tire a nal og co ntro l l oop is ra is ed to a v i rtu a l gro u n d ped es t a l e qua l to th e band g a p v o l t ag e (1 .23v) . 3. 10 ov ref th is re fere nc e is u s ed t o se t t he ou tpu t o v e r vo lt a ge s e t po in t. it i s c o m p are d to the v s in put pi n, w hi c h i s ty pi ca lly prop orti ona l to th e out put v o l t age bas ed o n a re sis t o r div i d e r . o v pr otec ti on, w h en e n ab le d, c a n b e s e t to a v a lu e for the p r ote c ti on o f s y s t e m ci rcu i try o r it c an be u s e d to ?rip p le ? re gul ate t he co nv erte r o u tp ut v o lt age for re po sit i on ing purpos es . for det ail s , r e fer to r e gi st e r 6- 4 . 3. 1 1 i ndependent gat e dr ive wit h p r og r a mm a b le d e l a y t w o i nde pen de nt low - s i d e g a te dr ive s are i n teg r ate d fo r sy nc hron ous app li cat i on s. pro g ra mm abl e de lay ha s be en im pl em ente d t o i m p r ove ef fi cie nc y and pre v e nt s hoo t-th roug h c u rre nt s . eac h gate dri v e ha s a n i nde pen den t e nab le in put c ont roll ed by th e pe1 re gis t er a nd p r ogra m m a b l e d ead tim e c ont rolled b y th e deadcon re g i ste r . http:///
? 2014 microchip technology inc. ds20005281a-page 21 mcp191 14/5 3. 12 t e mperat ure management 3 . 12 . 1 t h e r m a l s h u t do wn t o prot ec t t he mc p1 91 14 /5 from ov ertem p e r atu r e c ond iti ons , a 150 c jun c ti on tem per ature the r ma l s hut dow n has be en i m p l e m en ted . wh en t he j unc tio n te mp erat ure reac he s th is li mi t, th e d e vi ce di sab l e s th e o u tpu t dri v e r s. i n shu t do w n mo de , bot h pd r v an d sd r v ou tpu t s are di sa ble d and th e ov ertem p e r atu r e fl ag (o tif) is s e t in th e pi r 2 re gi ste r . w hen th e j unc tio n tem p e r atu r e is reduc ed by 20 c to 130c , the MCP19114 / 5 c an re s um e n or m al ou t pu t dr i v e swi t ch in g . 3.1 2 .2 t e mp er ature re porting th e m c p191 1 4 /5 h a v e a s e c ond on-c h i p tem p e r atu r e m o n i tor i ng circ ui t tha t ca n be read by the ad c th rough th e a n a l og te st mux. refe r to s e ct i o n 2 0 . 0 ?i n t er na l t e m p era t ure in dica tor m odul e? for d e t a i l s on thi s i n ter nal tem p e r atu r e m o n i tor i ng ci rcu i t. http:///
MCP19114/5 ds20005281a-page 22 ? 2014 microchip technology inc. 4.0 e l e ctr i c a l charac teris t ics 4. 1 absolute maximum rati n g s ? v in -v g nd (o pera t in g) . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . .. . .. .. .. .. .. .. .. - 0 . 3v t o +4 4v v in (tran s ie nt < 5 0 0 m s ) ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ... ... ..... ...... ...... ..... ......+4 8 v pdr v ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... . ( g n d - 0.3 v ) to (v dr +0 . 3 v ) sdr v ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... .... ...... ...... ..... ...... ...... ..... ...... ..... ...... . ..... . ( g n d - 0.3 v ) to (v dr +0 . 3 v ) v dd int e rna l l y g e n e rat e d ... ...... ..... ...... ...... ..... ...... .... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ... ... ..... ...... ...... ..... ..... +6. 5 v v dr ex tern all y g e n e ra ted .. ...... ..... ...... ...... ..... ...... .... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... .... .. ..... ...... ...... ..... ...+13. 5 v v o lt a ge on m c lr wi th r e sp ec t to g n d ..... ..... ...... .... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... -0.3 v to +13. 5v m a x i m u m vo lt a ge: an y o t her pin ... ...... ...... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... .... + ( v gn d - 0 .3 v) to (v dd +0 . 3 v ) m a x i m u m ou tput cu rren t su nk by an y s i n g le i/o p i n . ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ..... . ...... ..... .... 25 m a m a x i m u m ou tput cu rren t so urc e d by any s i n g le i/o pi n . . ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... .... 25 m a m a x i m u m cu rren t s unk by al l g p io ..... ...... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... . .... ...... ...... ..... .... 90 m a m a x i m u m cu rren t s ourc e d by al l g p io ..... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... .... . ...... ...... ..... .... 35 m a s tora g e t e mp erat ure ..... ..... ...... ..... ...... ...... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ... .. ...... ..... ..... -6 5c to +15 0 c m a x i m u m ju nc tio n t e m pera ture ... ...... ...... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... . .... ...... ...... ..... .. +15 0 c o p e r ati ng jun c t i on t e mp erat ure ... ...... ...... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ..... . ..... ..... -4 0c to +12 5 c esd p r ote c ti on on all pi ns (hbm).............. ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... .... .. ..... ...... ...... ..... ... 2 .0 k v esd p r ote c ti on on all pi ns (mm ) .... ...... ...... ..... ...... ..... ... .. ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ... ... ..... ...... ...... ..... ..... 20 0v ? n o t i ce : s t ress es a b o v e tho s e l i s t ed un der ?m axi m u m ra ti ngs? may cau s e p e rm ane nt dam ag e to the de vi ce. th is i s a s t re ss ratin g on ly and f unctio n a l ope rati on o f the d e v i c e at th os e or an y o t her c o n d it ion s ab ov e tho s e ind i c a ted in th e o pera t io nal l i s t in gs o f t his sp eci f ic ati on i s no t i m p l i ed. ex pos ure t o ma xi mu m rati ng c on diti on s for ex te nde d peri o d s ma y a f f e ct de vi c e r e li a b i l i t y . 4. 2 e l ectr i ca l charact eri s ti cs ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te rs sym . min . t y p . ma x. unit s c ond ition s in put in put v o l t ag e v in 4.5 ? 42 v in put q u ie sc ent c u rrent i q ?5 10 ma not swi t ch in g, + v sen =5 v sh ut d o w n cu rrent i sh d n ?3 0 15 0 a v in = 12v no te 1 li nea r regul ator v dd in tern al circ uitry bi as v o l t ag e v dd 4.7 5 5. 0 5. 5 vv in = 6 .0v to 4 2 v ma xi mu m e x te r n al v dd o u tp ut cu rren t i dd _o ut 35 ?? m a v in = 6 .0v to 4 2 v , no te 3 l i ne r egu la tion ? v dd- o ut / (v dd - o ut * ? v in ) -0 .1 0. 002 0. 1 %/ v ( v dd +1 . 0 v ) ? v in ? 20v no te 3 l oad r egu la tion ? v dd- o ut / v dd - o u t -0 .65 0. 1 +0 .65 %i dd _o u t = 1 ma to 2 0 m a no te 3 o u tp ut sho r t ci rcui t c u rrent i dd_ s c ?5 0 ? m a v in =( v dd +1 . 0 v ) no te 3 note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he inp u t-to -out put vo lt a ge d i f f ere n ti al at w h ich the ou tpu t v o lt age dro p s 2% b elo w it s no mi nal v alu e m ea s ur ed a t a 1v d i f f eren t ia l b etw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
? 2014 microchip technology inc. ds20005281a-page 23 mcp191 14/5 d r o pou t v o lt ag e v in -v dd ?0 . 3 0. 5 vi dd _o u t =2 0m a , no te 3 , no te 4 po wer su ppl y r e jec t io n r a tio psrr ld o ?6 0 ? d b f ? 1 000 h z , i dd _o u t =2 5m a c in =0f, c dd =1f li nea r regul ator v av d d in tern al anal og su ppl y v olt age v av d d ?4 . 0 ? v ba nd ga p v o lt a g e b g ? 1 . 23 ? v t r im me d a t 1. 0% t o le ran c e ba nd ga p to l e r a n c e bg tol -2 .5 ? +2 . 5 % in put uvl o v o lt age uvl o ra n g e uvl o on 4.0 ? 20 vv in fa lli ng uvl o on tr i p to l e r a n c e uvl o tol -14 ? 14 %v in fa lli ng uvlo tri p s e t t o 9v vin u v lo = 0x2 1h uvl o hys t e r e s i s uvl o hy s ? 4 ? % h y s t ere s i s i s b a s ed upo n the uvlo on s e tti ng uvlo tri p s e t t o 9v vin u v lo = 0x2 1h r e sol u ti on nbi t s ? 6 ? b i t s log ari t hm ic s t ep s uvlo com p a r a tor in put -to-o u t put de l a y td ? 5 ? s 100 ns ri se tim e to 1v ov erdri v e on v in v in > u vl o to f l ag se t in put o v lo v o lt a g e o v lo ra nge o v lo on 8.8 ? 44 vv in ri si n g ovl o on tr i p to l e r a n c e ovl o tol -14 ? 14 %v in ri si n g o v lo trip se t to 18 v vinovlo = 0 x 1 f h o v lo h y ste r es is ovl o hy s ? 5 ? % h y s t ere s i s i s b a s ed upo n th e ov lo on se tti ng o v lo trip se t to 18 v vinovlo = 0 x 1 f h r e sol u ti on nbi t s ? 6 ? b i t s log ari t hm ic s t ep s o v lo com p ara t or in put -to-o u t put de l a y td ? 5 ? s 100 ns ri se tim e to 1v ov erdri v e on v in v in > o vl o to fl ag se t 4. 2 e l ectr i ca l charact eri s ti cs (cont inued ) ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te r s sym . min . t y p . ma x. unit s c ond ition s note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he i n p u t-to -out put vo lt a ge d i f f ere n ti al at w h i c h the ou tpu t v o lt a g e dro p s 2% b e lo w it s no mi nal v a lu e m e a s ure d a t a 1v d i f f e ren t ia l b e tw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
MCP19114/5 ds20005281a-page 24 ? 2014 microchip technology inc. ou tp u t ov dac r e sol u ti on nbi t s ? 8 ? b i t s l in ea r d a c fu ll sc a l e rang e f sr 0 ? 2 * bg v to l e r a n c e o v r e f tol -10 ? +1 0 % f ul l sc al e, c o de = 0 x f f ou tp u t ov co m p a r a t o r ov hys t ere s i s o v hy s ?5 0 ? m v in put bia s c u rrent i bi as ? 1 ? a c o mm on-m o d e in put v o lt a ge r a n g e v cm r 0? 3 . 0 v no te 2 in put -to-o u t put de l a y td ? 2 0 0 ? n s no te 2 100 ns ri se tim e to 1v ov erdri v e on v s v s > o v t o fl ag set v olt a ge r e fer e n ce d a c (v re f ) r e sol u ti on nbi t s ? 8 ? v /v lin e a r d a c fu ll sc a l e rang e f sr bg ? 2 * b g v ped e s t al s e t to bg v olt a ge r e fer e n ce d a c (v re f 2 ) r e sol u ti on nbi t s ? 8 ? b i t s l in ea r d a c fu ll sc a l e rang e f sr 0 ? bg v si nk curren t i si n k -3 ?? m a v re f 2 =0 v , r l =3 0 0 ?? to bg so urc e c u rr ent i s o urc e 3 ?? m a v re f 2 =b g , r l =3 0 0 ?? to g n d to l e r a n c e v r e f 2 to l -10 ? +1 0 % f ul l sc al e, c o de = 0x ff curre n t se n s e am plifi e r (a2 ) am pl ifi e r psrr psrr ? 65 ? d b v cm =2 * b g c l ose d l oop v o lt a ge ga in a2 vc l ?1 0 ? v / v r l =5 k ? to 2 . 04 8v , 100 m v < a 2 < v av d d ? 100 mv , v cm =b g l o w - le ve l o u tp ut v ol ?5 0 0 ? m v r l =5 k ? to 2.0 4 8v ga in b a n d w idt h pro duc t gb w p ? 1 0 ? m h z v av d d =4 v in put im ped anc e r in ?1 0 ? k ? si nk curren t i si n k -3 ?? m a i sp =i sn =g n d r l =3 0 0 ? to 2 * bg so urc e c u rr ent i s o urc e 3 ?? m a i sp =i sn =g n d r l =3 0 0 ? to g n d 4. 2 e l ectr i ca l charact eri s ti cs (cont inued ) ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te rs sym . min . t y p . ma x. unit s c ond ition s note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he inp u t-to -out put vo lt a ge d i f f ere n ti al at w h ich the ou tpu t v o lt age dro p s 2% b elo w it s no mi nal v alu e m ea s ur ed a t a 1v d i f f eren t ia l b etw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
? 2014 microchip technology inc. ds20005281a-page 25 mcp191 14/5 c o mm on mo de r a nge v cmr gnd ? 0.3 ? v bg +0.3 v note 2 c o mm on mo de r e jec t io n r a tio cmrr ? 7 0 ? d b in tern al fee dba ck re s i sto r r fb _ i n t ?5 ? k ? in tern al fee dba ck re s i sto r t o l r f b _i nt _tol ?2 ? % t ri m m e d pe des t al v o lt age pe des t a l v o lt ag e le v el vzc ? bg ? v error am plifie r (ea) in put o f fs et v o lt age v os ?2 ? m v c o mm on mo de r e jec t io n r a tio cmrr ? 6 5 ? d b v cm = 0 v to bg op en - l oo p v o lta g e ga in a vo l ?7 0 ? d b no te 2 lo w - l ev el cl am p va lu e v ol bg - 0 .3 5 bg - 0 .2 2 bg - 0 . 1 vr l =5 k ? to 2 . 04 8v ga in b a n d w idt h pro duc t gb w p ? 3 . 5 ? m h z erro r am pli f ie r sin k c u rrent i si n k -3 ?? m a v re f =b g , i fb =i co m p r l =1 5 0 ? to 1 . 5 * bg erro r am pli f ie r so urc e c u rrent i s o urc e 3 ?? m a v re f =2 * b g , i fb =i co m p r l =1 5 0 ? to 1.5 * bg ma xi mu m e r r o r am pl ifi e r o u tp ut h i gh -lev el cl a m p v ea_ ma x ? 2 * b g ? v ea o u tp ut c l a m p ed t o 2* b g v o l t a g e pe ak c u rr e n t se nse inpu t ma xi mu m p r i m a r y c u rrent sens e si gna l v o lt a g e v ip _ m a x ?b g 1 . 5 v no te 2 p w m co m p ar at o r in put -to-o u t put de l a y td ? 2 0 ? ns no te 2 4. 2 e l ectr i ca l charact eri s ti cs (cont inued ) ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te r s sym . min . t y p . ma x. unit s c ond ition s note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he i n p u t-to -out put vo lt a ge d i f f ere n ti al at w h i c h the ou tpu t v o lt a g e dro p s 2% b e lo w it s no mi nal v a lu e m e a s ure d a t a 1v d i f f e ren t ia l b e tw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
MCP19114/5 ds20005281a-page 26 ? 2014 microchip technology inc. pe ak c u rr e n t le adi ng ed ge bla n ki ng r e sol u ti on leb ? 2 ? bi t s bl ank in g t i me ad jus t ab le r ang e le b ra n g e 0 ? 25 6 n s 4 -s tep prog ram m a b le r ang e (0, 50,1 00, an d 200 n s) no te 2 offse t adju stme nt (i p sense) re s o l u ti o n o s ad j ?4 ? b i t s o ffs et a d ju st m e n t r a nge os a d j _ ra ng e 0? 7 5 0 m v o ffs et a d ju st m e n t st e p s i z e os ad j_ st ep ? 5 0 ? m v l i ne ar s t e ps adj u st a b le slope comp ens a tion re s o l u ti o n sc re s ? 6 ? b i t s log s t ep s sl ope m 4 .1 ? 4 3 2 .5 m v /s sl ope s tep siz e sc st ep ? 8 ? % log s t ep s ra m p set po in t to l e r a n c e m to l ? 1 3 0 % de satu r a t ion detec t ion c o mp a r ator in put o f fs et v o lt age v os ? 1 ? mv t r im me d, 5 bi t s adj u s t ab le in put bia s c u rrent i bi as ? 1 ? a inte rna l circ ui t dep end en t c o mm on-m o d e in put v o lt a ge r a n g e v cm r gn d ? 0. 3 v ? 2 . 7 v no te 2 in put -to-o u t put de l a y td ? 2 0 ? ns v dr uvlo v dr uvl o (2 .7v v dr fa lli ng ) v d r _ u v lo _ 2. 7_ f 2. 4 5 ? 2 .9 v v dr uvl o (2 .7 v dr ri si n g ) v dr_ uv lo _2. 7_ r 2. 6 8 ? 3 .23 v v dr uvl o (2 .7v) h y st eres is v dr_u v lo 2. 7 hy s 19 0 ? 4 15 m v v dr uvl o (5 .4v v dr fa lli ng ) v d r _ u v lo _ 5. 4_ f 4.7 ? 5 . 96 v v dr uvl o (5 .4v v dr ri si n g ) v dr_ uv lo _5. 4_ r 5. 1 5 ? 6 .56 v v dr uvl o (5 .4v) h y st eres is v dr_u v lo 5. 4 hy s 38 0 ? 8 30 m v 4. 2 e l ectr i ca l charact eri s ti cs (cont inued ) ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te rs sym . min . t y p . ma x. unit s c ond ition s note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he inp u t-to -out put vo lt a ge d i f f ere n ti al at w h ich the ou tpu t v o lt age dro p s 2% b elo w it s no mi nal v alu e m ea s ur ed a t a 1v d i f f eren t ia l b etw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
? 2014 microchip technology inc. ds20005281a-page 27 mcp191 14/5 o u tpu t drive r (pdr v a nd sdr v ) pdr v /sdr v gate d r i v e sourc e r e sis t a n ce r dr- s rc ?? 13 . 5 ? v dr =4 . 5 v no te 2 pdr v /sdr v gate d r i v e sink r e sis t a n ce r dr- s i nk ?? 12 ? v dr =4 . 5 v no te 2 pdr v /sdr v gate d r i v e sourc e c u rrent i dr- s r c ?0 . 5 ? a v dr =5 v v dr =1 0 v no te 2 ?1 . 0 ? pdr v /sdr v gate d r i v e sink c u r r ent i dr- s i nk ?0 . 5 ? a v dr =5 v v dr =1 0 v no te 2 ?1 . 0 ? de a d t i m e adju s t m e nt re s o l u ti o n d t re s ?4 ? b i t s d e ad t i me ad jus t ab le rang e dt ra n g e 16 ? 2 56 n s d e ad t i me s t ep si z e dt st ep ? 16 ? ns lin ea r s t ep s d e ad t i me to l e r a n c e dt tol ? 8 ? n s o s c illa tor/pwm in tern al os ci ll ator fr equ ency f os c 7.6 0 8. 0 0 8. 4 0 mhz swi t c h ing fr equ ency f sw ?f os c /n ? m hz swi t c h ing fr equ enc y r ang e se lec t n4 ? 2 5 5 ? f max =2 m h z a/d co nv e r te r (adc) cha r a c te ris t ic s re s o l u ti o n n r ?? 1 0 b i t s in teg r al error e il ?? 1 l s b v re f _ a dc =v av d d d i f f e r ent ial error e dl ? ? 1 lsb n o m i s s i ng cod e i n 1 0 bi t s , v re f _ a dc =v av d d o ffs et e r r o r e of f ? + 3.0 + 5. 0 l sb v re f _ a dc =v av d d gai n erro r e gn ? 2 5 l s b v re f _ a dc =v av d d r e f e r e nc e v o lta g e v re f _ a dc ?v av d d ?v fu ll -scale r a nge fsr a/ d gnd ? v av d d ? 4. 2 e l ectr i ca l charact eri s ti cs (cont inued ) ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te r s sym . min . t y p . ma x. unit s c ond ition s note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he i n p u t-to -out put vo lt a ge d i f f ere n ti al at w h i c h the ou tpu t v o lt a g e dro p s 2% b e lo w it s no mi nal v a lu e m e a s ure d a t a 1v d i f f e ren t ia l b e tw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
MCP19114/5 ds20005281a-page 28 ? 2014 microchip technology inc. g p io pin s ma xi mu m gp i o si nk curren t i si n k_ g pi o ?? 9 0 m a no te 5 ma xi mu m gp i o so urce c u rr ent i s o ur ce _g p i o ?? 3 5 m a no te 5 g p io w eak pu ll-u p c u rrent i pu l l - u p_ g pi o 50 2 50 4 00 a g p io in put low vo l t a g e v gp io _ il gnd ? 0. 8 v i/o port with ttl bu f fe r , v dd =5 v gnd ? 0.2 v dd v i/o port with sch m i t t t r ig ger b u f f er , v dd =5 v gnd ? 0.2 v dd vm c l r gpio input high vo l t a g e v gp io _i h 2.0 ? v dd v i/o port with ttl bu f fe r , v dd =5 v 0. 8v dd ? v dd v i/o port with sch m i t t t r ig ger b u f f er , v dd =5 v 0. 8v dd ? v dd vm c l r gpio outp ut l o w vo l t a g e v gp io _o l ?? 0. 12 v dd vi ol =7 m a , v dd =5 v g p io o u tp ut hi gh vo l t a g e v gp io _o h v dd -0. 7 ? ? v i oh =2 . 5 m a , v dd =5 v g p io in put l eak ag e c u rre nt gpi o _ i il ? 0 . 1 1 a n ega tiv e c u rre nt i s defi n e d as cu rren t so urce d by the pin . th erma l shu t dow n th erm a l shu t dow n t sh d ?1 5 0 ? c th erm a l shu t dow n hys t e r e s i s t s h d_hy s ?2 0 ? c 4. 3 ther m a l sp eci fi cat ions pa ra m e te rs sy m . m i n . t y p. ma x . u n it s t e m p era t ure ra nges s p ec if i e d t em pe r at u r e r a n ge t a -40 ? +1 25 c o pe r ati ng jun c t i on t e mp erat ure r a ng e t j -40 ? +1 25 c m ax i m um ju nc tion t em pera t ure t j ?? + 1 5 0 c s t ora g e t e mp erat ure r a nge t a -65 ? +1 50 c th er ma l pac k a g e r e sist anc e s th erm a l r e s i s t anc e, 24l -q fn 4x 4 ? ja ?4 2? c / w th erm a l r e s i s t anc e, 28l -q fn 5x 5 ? ja ? 35. 3 ? c/w 4. 2 e l ectr i ca l charact eri s ti cs (cont inued ) ele c tric al s p ec ifica t ions : un le ss ot h e r w i s e n o t e d, v in = 12v , f sw =1 5 0 k h z , t a =+ 2 5 c , bo ldfa c e s pe c if ic atio ns ap p l y ov er t h e t a ran ge of -4 0c to +12 5 c param e te rs sym . min . t y p . ma x. unit s c ond ition s note 1 : re f e r to sec t ion 15. 0 ?pow er-dow n m ode (slee p ) ? . 2: en su red b y des ig n, no t p r odu ct ion tes t ed . 3: v dd is th e v o lt age pre s e n t a t th e v dd pi n. 4: d r o pou t v o lt a g e is de fine d a s t he inp u t-to -out put vo lt a ge d i f f ere n ti al at w h ich the ou tpu t v o lt age dro p s 2% b elo w it s no mi nal v alu e m ea s ur ed a t a 1v d i f f eren t ia l b etw ee n v in and v dd . 5: th e v dd ld o w i ll l i m i t th e to t a l s o u r ce cur r ent t o a m a x i m u m o f 35 ma. indi vi dua ll y ea ch pin can so urc e a ma xi mu m o f 1 5 ma . http:///
? 2014 microchip technology inc. ds20005281a-page 29 mcp191 14/5 5 . 0 d igit al e l ectrical chara cte r i s tics 5. 1 t imi ng par a m e t e r symbology th e tim i ng p a ram e te r s y m b o l s ha ve be en cre a te d w i th o ne o f th e fo ll ow in g fo rma t s: 1 . tp ps2p ps 3. t cc: s t (i 2 c sp ec ifi c at ion s o n l y ) 2. t pp s 4. t s (i 2 c sp ec ifi c at ion s o n l y ) t f f re qu enc y t t i me l o w e rc as e l e tte rs ( pp) and the i r m e a n in gs : pp cc ccp1 o sc osc1 ck cl k o ut rd rd cs cs rw rd or wr di s d i s c s c k do sdo ss ss d t da t a i n t0 t0 cki io i/o port wr wr mc mclr u p pe r c a s e le t t e r s an d t h ei r me an i n g s : s ff a l l p p e r i o d hh i g h rr i s e i i n v a lid (hi gh-i m p e d anc e) v v ali d l l ow z h ig h-i m p eda nc e i 2 c on ly a a ou t p ut ac ce ss h i gh h i gh buf b u s f r ee lo w l o w t cc: s t (i 2 c s pec ifi c a t io ns onl y) cc hd ho l d su se tu p st d a t d a t a inp ut hol d s t o st op co ndi tio n st a s t a r t co ndi tio n http:///
MCP19114/5 ds20005281a-page 30 ? 2014 microchip technology inc. figure 5-1: lo a d conditions 5. 2 ac c h aract eri s ti cs: mcp191 14 (i ndust r i a l, ext e nded) figure 5-2: ex tern al clock t i ming t a ble 5 - 1 : ex tern al clock t i ming re quire m e n t s para m. no . sy m. c h ar ac ter i sti c m i n. t y p. ? ma x. uni t s c o nditio n s f os c os c ill ato r freq uen cy ( 1 ) ?8 ? m h z 1t os c o s c i l l ato r per i od ( 1 ) ? 250 ? n s 2t cy in s t r u ct i o n cy cl e t i me ( 1 ) ?t cy ? ns t cy = 4 * t os c * t h e s e p a ram e t e rs are ch arac teri ze d b u t n o t t e s t ed. ? d a ta i n ? t y p . ? c o l u m n i s a t v in =1 2 v ( v dd = 5 v), 25c u n l e ss ot herw i se st a t ed . th ese p a r am ete r s a r e fo r d esi gn gui da nce on ly an d are no t te ste d. note 1 : in str u ct ion cy c l e p e r i od ( t cy ) eq ual s f our t i m es the in put os cil l a t or ti me ba se pe riod . all s pec ifi ed va lue s a r e b a se d o n c har act e riz a ti on dat a fo r th at p a rti c u l ar o s c i l l at or ty pe un der s t a nda rd o pera t in g c ond iti ons w i th th e d ev i ce ex ec uti ng co de. v dd /2 c l r l pi n p in v ss v ss c l r l =4 6 4 ? c l = 5 0 p f f o r al l g p io pi ns l oad cond iti on 1 load condition 2 os c q4 q1 q 2 q3 q4 q1 1 2 http:///
? 2014 microchip technology inc. ds20005281a-page 31 mcp191 14/5 figure 5-3: i/o t i ming t able 5 - 2 : i/o t i ming re quire m e n t s para m. no . s y m. c h a r ac t e r i st i c m i n . t y p . ? m a x . unit s c o nditio n s 17 t o s h 2io v o s c 1 ? ( q 1 cy cl e) t o port out valid ? 50 7 0* ns 18 t o sh 2i oi o s c 1 ?? (q 2 c y c l e ) to port inp u t in va lid (i/o i n ho ld tim e ) 50 ? ? ns 1 9 t i ov 2 o s h p o r t i n pu t v a li d t o os c 1 ?? (i/o i n s e tu p ti me ) 20 ? ? n s 20 t i or port out put ris e ti me ? 3 2 4 0 n s 21 t i of port out put fal l ti me ? 1 5 3 0 n s 22 * t in p i n t pi n h i gh or l o w t i me 25 ? ? n s 23 * t ra b p gpi o in terru pt-o n-c han ge ne w inp u t leve l tim e t cy ?? n s * t h e s e p a ram e t e rs are ch arac teri ze d b u t n o t t e s t ed. ? d at a i n ?t yp? co lum n i s at v in =1 2 v ( v dd =5 v ) , 2 5 ? c un le ss oth erw is e s t a t ed. osc i/o pin (inp ut) i/o pin (output) q4 q1 q2 q3 17 20, 21 22 23 19 18 ol d v a lu e new va lue http:///
MCP19114/5 ds20005281a-page 32 ? 2014 microchip technology inc. figure 5-4: res e t , w a tc hdog t i me r , os ci l l ator st art-up t i m e r and p o we r-up ti m e r ti m i n g figure 5-5: brow n - o ut re s e t t i ming a nd chara cteris tics v dd mclr inte rna l por pwr t ti m e - o u t osc t i me -out inte rna l re se t w a tc hd og timer reset 33 32 30 31 34 i/o pins 34 v dd b vd d b vh y b vd d +b vh y res e t (due to bo r) (device not in brown-out reset) (device in brown-out reset) 64 ms time out (if pwrte) 35 http:///
? 2014 microchip technology inc. ds20005281a-page 33 mcp191 14/5 figure 5-6: timer0 and timer1 external clock timing t able 5 - 3 : res e t , w a tc hdog t i me r , osci l l ator st art-up t i m e r , and pow e r-up t i m e r require m e n t s para m. no . s y m . c h a r ac t e r i st i c mi n . t y p. ? m a x . un it s c ond itions 30 t mc l mcl r p u l s e wi dt h ( l ow ) 2 ? ? ? sv dd = 5 v , -40c to +8 5c 31 t wd t w a tc hdo g t i m e r t i m e -ou t pe rio d (no pres c a ler) 71 8 3 3 m s v dd = 5 v , -40c to +8 5c 32 t os t o s ci lla tio n s t art - up t i m e r pe rio d ? 1 024 t os c ?? t os c = o s c 1 pe r i od 33 * t pw r t po wer u p t i m e r peri od (4 x t wd t ) 28 7 2 132 ms v dd = 5 v , -40c to +8 5c 34 t ioz i/ o h i gh - i mp ed an c e f r om mcl r l o w or w a tc hdo g t i me r re s e t ?? 2 . 0 s b vd d b r ow n - ou t r e s e t v o l t ag e 2 . 0 ? 2 .3 v b vh y b r ow n - ou t h y s t er e s i s ? 10 0 ? m v 35 t bc r bro w n-o u t r e set pul se w i d t h 1 00 * ? ? s v dd ? b vd d (d 005 ) 48 tc ke z- tm r del a y f r om cl oc k e d g e t o ti me r i nc r em ent 2t os c ?7 t os c * t h e s e p a ram e t e rs are ch arac teri ze d b u t n o t t e s t ed. ? d at a i n ?t yp? co lum n i s at v in =1 2 v ( v dd =a v dd = 5 v ) , 25 c u n l e ss o t he r w i s e stat e d . t h es e par a m e t er s a r e fo r de si gn g ui dan ce onl y and are not tes t ed . 41 42 40 t0cki tmr0 48 http:///
MCP19114/5 ds20005281a-page 34 ? 2014 microchip technology inc. figure 5-7: pw m t i mi ngs t a ble 5 - 4 : t i m e r0 ex tern al clock re q u irem en t s pa r a m. no. sym. c h ar ac ter i sti c min . t y p. ? ma x. uni t s c ond ition s 40* t t 0h t 0 ck i hi g h p u l s e w i d t h n o pres caler 0 . 5 t cy +2 0 ? ? n s wi t h pres cal e r 10 ? ? ns 41* t t 0l t 0 c k i low pulse w i d t h n o pres caler 0 . 5 t cy +2 0 ? ? n s wi t h pres cal e r 10 ? ? ns 42* t t 0p t 0 ck i period g r eat er of : 20 or ? ? ns n = presc a l e val u e ( 2 , 4 , .. ., 2 5 6 ) * t h e se paramet ers are charac t e r i z ed but no t t e st ed. ? d at a in ? t yp. ? c o l u mn i s at v in = 12v , 2 5 c unless ot herwise st a t ed. t hese p a ram e t e r s a r e f o r design guidanc e only and a r e not t e st ed. t a b l e 5- 5: p w m r e qu i r em en t s pa r a m. no. s y m . c h a r ac t e r i st i c m i n. t y p . ? ma x . unit s c onditi ons 53* t c c r pw m (cl kpin) ou tpu t fa ll t i m e ? 1 0 2 5 n s 54* t c c f pw m (cl kpin) ou tpu t fa ll t i m e ? 1 0 2 5 n s * t h e s e p a ram e t e rs are ch arac teri ze d b u t n o t t e s t ed. ? d at a i n ?t yp? co lum n is at v in =1 2 v ( a v dd = 4 v), 25c unl ess o t her w i se st ate d . pa ram e te rs a r e f o r d esi gn gui da nce on ly an d are no t te ste d. t cy 40 + n ---- --- -- -- -- -- -- -- -- - - no te : re fer to fi gu re 5- 1 fo r lo ad c o n d it ion s . 53 54 pwm (clkpin) http:///
? 2014 microchip technology inc. ds20005281a-page 35 mcp191 14/5 t able 5 - 6 : mcp 191 1 4 /5 a / d co nv erte r (adc) cha racter istics s t and a rd o p era t ing conditi ons (unle ss othe r w is e s t ated ) op e r ati ng tem pera t ure - 40 c ? t a ? +12 5 c para m. no . sym. c h ar ac ter i s t ic m i n. t y p. ? ma x. unit s c ondi tions ad01 n r r e s o l u t i o n ? ? 10 bi ts b i t ad02 e il i n teg r al error ? ? ? 1l s b a v dd = 4 . 0 v ad03 e dl d i f f e r ent ial error ? ? ? 1 l sb n o m i s s i ng co des to 10 bi t s av dd =4 . 0 v ad04 e of f o f fse t erro r ? +1 .5 +2.0 lsb a v dd =4 . 0 v ad07 e gn gai n erro r ? ? ? 1l s b a v dd =4 . 0 v ad07 v ai n f ull -sca le r ang e a gn d ?a v dd v ad08 z ai n r e co mm end ed imp e d anc e of a n al og v o l t ag e s o u r ce ?? 1 0 k ? * t h e s e p a ram e t e rs are ch arac teri ze d b u t n o t t e s t ed. ? d a t a in ?t y p . ? c o lu mn is at v in =1 2 v ( a v dd = 4 v), 25c u n l e ss o t her w i se st ate d . t hes e p a rame t e rs are fo r de si gn gui dan ce onl y and are not tes t ed . note 1 : t o t a l ab so lute erro r inc l u des i n teg r al , di f f e r en tial , o f fs et a n d gai n e rrors . 2: th e a/ d co nve r si on res u lt nev er dec rea s e s wi th an i n cr eas e i n th e i npu t v o lt age an d has no m i s s i ng c ode s. 3: w hen ad c is of f, i t wi l l n o t c o n s u m e any c u rren t o t her tha n le ak age c u rren t. t he p o w e r- dow n cu rrent s pec if ica t io n i n c l ud es any s u c h l eak ag e fro m t he ad c mo dul e. t able 5 - 7 : mcp 191 1 4 /5 a / d conv ers i on re quire m e n t s s t and a rd o p era t ing conditi ons (unle ss othe r w is e s t ated ) o p e r ati ng tem pera t ure - 40 c ? t a ? +12 5 c pa ram. no. sy m. c h ar ac ter i sti c m i n. t y p. ? ma x. unit s c o nditi ons ad 1 30* t ad a/d cl o c k pe r i o d 1 . 6 ? 9 . 0 s t os c -b as ed a/d in te rn a l rc os c i lla tor p e rio d 1.6 4 . 0 6 . 0 s a dcs<1:0 > = 11 (adrc mo d e ) ad13 1 t cnv c o nv ersi on t i m e (n ot inc l u d in g ac qui si tio n t i me) ( 1 ) ?1 1? t ad se t go/done bit to new data in a/d r e s u lt regi ste r s ad 1 32* t ac q ac qui si tio n t i m e ? 1 1. 5 ? s ad 1 33* t amp amp lif ier settl ing ti m e ?? 5 s ad13 4 t go q4 to a/ d cl o c k s t a r t ? t os c /2 ? ? * t h e s e p a ram e t e rs are ch arac teri ze d b u t n o t t e s t ed. ? d a t a in ? t yp . ? co lu mn is a t v in =1 2 v ( v dd =a v dd = 5 v), 25c unl es s oth e rw is e st a t ed . th es e p a ra me ters a r e fo r de si gn g ui dan ce onl y and are not tes t ed . note 1 : adr esh a nd ad r e s l reg i s ters m a y be read on the fol l o w i n g t cy cy cl e . http:///
MCP19114/5 ds20005281a-page 36 ? 2014 microchip technology inc. figure 5-8: a/d c o nv e r sion t i mi ng 131 130 132 bsf adcon0 , go q4 a/ d cl k a/ d da t a adres adif go sam ple o l d_ da t a sam pling st o p ped new_data 98 7 32 1 0 1/2 t cy 6 134 done note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. http:///
? 2014 microchip technology inc. ds20005281a-page 37 mcp191 14/5 6.0 c onfig u ring th e m c p1 91 14 /5 th e mc p1 91 14 /5 are anal og c ont roll e r s w i th a dig i t a l p erip hera l . thi s me ans th at dev ic e co nfig ura t ion i s h and led th rou gh reg i st er set t in gs in ste ad of ad din g e x te rnal co mp one nt s . th ere a r e s e v e ral int e rna l c onf igu r ab le c om p a r ato r mo du les us ed to i nte rfac e a nal og ci rcu i t s to di git al pro c es s i ng th at a r e ver y s i m i l ar to a s t and ard c o m p ara t or mo dul e foun d in ma ny pic p r oc ess o rs to day (i .e. pic 16f 182 4/1 828 ). th e fo ll ow in g sec t i ons d et a il h ow to se t the an al og co ntro l re gis t er s fo r al l th e c o n f ig urable p a ra me ters . 6. 1 i nput underv o l t a ge and overvo lt age lockou t ( u vlo and o v lo) v i n c o n i s t h e co mpar a t or co nt r o l r e g i s t er f o r bo t h t h e v i n u v lo an d v i n o v l o r e g i s t er s . i t co n t a i ns t h e e nab le bit s , t he pol arit y e dge de tec t io n b i t s an d th e s t at us out put bi t s for bot h p r ote c ti on ci rcu i t s . th e i n ter r upt fla g s and i n t he pir 2 re gis t er are ind epe nde nt o f th e en ab le < u vlo e n > an d b i t s i n th e vincon re g i ste r . th e un derv o l t ag e lo ck ou t s t atu s o u tp ut b i t i n th e vin c o n re gis t er ind i c a tes i f an u v lo ev en t ha s o c c urre d. t he o v e r vo lt a ge lo ck out st atu s o u tpu t b i t in th e vi n c o n r egi ste r indi ca tes i f an o v lo e v en t h a s oc cur r ed. th e vin u v lo regi st er co nt a i ns the d i gi t a l v a l u e th at s e t s th e i npu t u nde rvo l t a ge lock out. u v lo h a s a rang e of 4v t o 20 v . wh en the inp u t v o l t ag e on the v in pi n t o th e m c p19 1 1 4 /5 is be low t h is pr ogra m m e d le vel an d th e bit in t he vi n c o n regis t er is s e t , both pd r v a nd sd r v g a te d r iv ers a r e di sa ble d . th is b i t i s au tom at i ca ll y cle are d w h en the m c p191 1 4/5 v in v o lt age ris e s ab ov e th is pro g ram m ed l e v e l. th e vi n o vl o regi st er c o n t ai ns the di git al va lue th at s e t s the in put ov ervolt age loc k out. ov lo has a rang e of 8. 8v to 4 4 v . w hen th e i npu t v o l t ag e o n t he v in pi n to th e m c p19 1 14/5 i s abo ve thi s pro g ram m e d leve l an d th e < o vlo e n> b i t in th e vinco n reg i st er is s e t, bo th pd r v a nd sd r v g a te d r iv ers a r e di sa ble d . th is b i t i s au tom at i ca ll y cle are d w h en the m c p191 1 4/5 v in v o lt age dro p s bel ow th is prog ram m e d l e v e l. r e fer to fi gur e 2 7 - 1 . note : th e u v lo if and o v l o if i n te rrupt fl ag bi t s are s e t w h en a n in terru pt c o nd iti o n oc c u rs , re gard l es s of the s t at e o f i t s c o rre spo ndi ng e nab le b i t or th e g l ob al en abl e bi t (g ie) i n t he i n tc on regi ste r . regis t er 6-1: vi ncon: uvlo and ov lo comp a rator control regis t er r/w -0 r -0 r/w -0 r/ w -0 r/w -0 r -0 r/w -0 r /w -0 uvlo en uvl oout u vl oi nt p u vlo i nt n o vl oen o v l oo ut ovl o i n t p ovl o i n t n bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ?0 ? x = bi t i s u n c han ged x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 uv l o e n: u v lo co m p a r ator mo dul e l ogi c e nab le bit 1 = u vl o c om p ara t or mo dul e l ogi c e nab le d 0 = u vl o co m p ara t or mo dul e l ogi c d i s abl ed bi t 6 uv l o o u t : u n d e rv olt a ge loc kou t s t a t us o u tp ut 1 = u vl o ev ent has o c c u rred 0 = n o uv lo e v en t h as oc cur r ed bi t 5 uv l o i n t p : u v lo c o mp arat or in terru pt o n po si tiv e g o i ng edge ena b le bi t 1 = t he u v lo if i n te rrupt fla g w i l l b e s e t upo n a pos it ive go ing ed ge of th e u v l o 0 = n o uv lo if int e rrup t fl ag w i ll be se t upon a po si tiv e g o in g e dge of the u v lo bi t 4 uv l o i n t n : u v lo co m p a r ato r in terru pt o n ne g a ti ve g o in g ed ge en ab le b i t 1 = t he u v lo if i n te rrupt fla g w i l l b e s e t upo n a neg ati v e goi ng edg e o f th e u v lo 0 = n o u v lo if int e rrup t fl ag w i ll be se t up on a ne gat iv e go in g ed ge of the u v l o http:///
MCP19114/5 ds20005281a-page 38 ? 2014 microchip technology inc. bi t 3 ov l oe n : o v l o c o mp ara t or m od ule lo gic en ab le b i t 1 = o vl o c o mp ara t or m od ule lo gic e nab led 0 = o vl o c o mp ara t or m o d u le lo gic d i sa bl ed bi t 2 ov l oo u t : ov erv o l t ag e l o ck ou t s t atu s ou tpu t bi t 1 = o vl o eve nt has oc cu rred 0 = n o o v lo ev en t ha s o c c u rre d bi t 1 o v lo i n tp : o v lo co m p a r ato r inte rrup t on pos i ti ve g o in g ed ge enab le bit 1 = t he ovl o if in terru pt flag wi l l b e s e t u pon a pos iti v e go ing edg e o f th e o v lo 0 = n o o v lo if i n te rrup t fla g wi ll be s e t upo n a po sit i v e go in g ed ge of the o v l o bi t 0 o v lo i n tn : o v lo co m p ar ator inte rrup t on nega tiv e g o ing edg e ena b l e bi t 1 = t he ovl o if in terru pt flag w i l l b e s e t u pon a neg ativ e goi ng edg e o f the o v lo 0 = n o o v lo if i n te rrupt fla g w i ll be s e t upo n a ne gati v e go ing ed ge o f th e o v lo regis t er 6-2: vi nuvlo: inp u t unde rv o l t a ge lockout r e gis t er u-0 u -0 r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x ? ? u vl o5 uvlo4 u vlo3 uvl o 2 u vl o1 uvlo0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 u n i m pl e m en t e d: rea d as ? 0 ? bi t 5- 0 u v l o <5 : 0 >: u n d e rv olt age lo ck out c onf igu r ati on b i t s u v lo (v) = 3 . 54 72 * ( 1.0 2 8 5 n ) w h e r e n = the de ci ma l val u e w r it ten to th e vin u v lo r e gis t er fro m 0 to 6 3 reg i s t er 6- 3: vi nov l o : inpu t o v e r volt a g e lockout re giste r u-0 u -0 r/w - x r /w -x r/w - x r /w -x r/w -x r/w-x ? ? o v l o5 o v lo 4 o v l o 3 ov l o 2 o v l o1 ov l o 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 u n i m pl e m en t e d: rea d as ? 0 ? bi t 5- 0 o v lo <5 : 0 >: o v erv o l t ag e l o c k ou t c o n f ig urat ion bi t s o v lo( v ) = 7. 4 8 4 7 * ( 1 . 0 28 6 n ) where n = the decimal value written to the vinovlo register from 0 to 63 regis t er 6-1: vi ncon: uv lo and ov lo co mp arator c o n t r o l re g i ste r (continu ed) http:///
? 2014 microchip technology inc. ds20005281a-page 39 mcp191 14/5 6. 2 o ut put o v ervol t age prot ecti o n t h e mc p 1 9 1 14 / 5 f e at u r e ou t p u t ov er v o lta g e p r ote c ti on. th is f eatu r e al so ut ili ze s a co mp ara t or mo du l e s i m i l a r t o t h e s t an d a r d p i c co mpar a t or m o d u l e . th is is us ed t o pre v e n t th e p o w e r s y s t em fro m b e in g d am age d w h en the lo ad is di sc on nec ted . th e o v r e fc o n reg i s t er c o n t ain s t he d i g i t a l v a lu e th at s e t s th e a nal og d a c vo lt a ge at t he i n v e rti ng inp u t o f th e c om p a r ator . by co mp arin g th e d i vi de d do w n po w er t r ai n o u t p ut vo lta g e c o nn ec t e d t o t h e n o n - in v e r t i n g i npu t (v s ) of t he com p a r ato r w i t h th e o v r e f refer enc e v ol t age , the u s er w i l l kn ow w hen a n ov erv olt age e v e nt h a s oc cur r ed a n d ca n a u tom a t i ca ll y t a ke ac tio n . t h e ov c o n r e gi st e r c o n t ai ns t h e in t e r r u pt fl a g po la r i ty an d o v e nab le bi t s a l on g w i th th e out put s t atu s bi t jus t as vin c o n doe s f o r the in put v o l t ag e u v lo an d o v lo . wh en bi t i n the o v c o n re gi ste r i s s e t an d a n ov erv ol t ag e oc cu rs, the co ntro l lo gic w i l l au tom a t i ca ll y set th e s e c o n dary g ate dr ive o u tp ut (sd r v) h i gh a nd se t the pr im ary ga te dri v e o u tp ut (pdr v) low . note : th e o v if int e rrup t fl ag bi t is s e t wh en an in terr upt c ond iti on o c c u rs , rega rdl e s s of th e s t a t e of it s c o rre spo n d i ng en abl e bit or th e gl oba l enab le bi t (g ie) in th e i n tc on re gis t er . regis t er 6-4: ovcon: outp ut o v e r volt ag e com p arator control re giste r u-0 u -0 u-0 u -0 r/w -0 r -0 r/w - 0 r /w -0 ? ? ? ? o ven ovo u t o vintp o vintn bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 u n i m pl e m en t e d: rea d as ? 0 ? bi t 3 o ven : ov c o mp ara t or o u tp ut e nab le bit 1 = o v c o mp ara t or o u tp ut i s e nab le d 0 = o v c o mp ara t or o u tp ut i s n o t en abl ed bi t 2 ov o u t : o u t p ut ov er v o l t ag e s t at u s ou t p u t bi t 1 = o u t put o v er vol t ag e h as oc cu rred 0 = n o o u tp ut o v erv o lt age has o c c u rred bi t 1 ov i n t p : o v c o m p a r ator inte rrup t on pos i ti ve g o in g ed ge e nab le b i t 1 = th e o v if int errup t fl ag w ill be se t up on a po si tiv e g oin g e dge of the ov 0 = no ovi f in terru pt f l ag wi l l be s e t u pon a p o s i ti ve goi ng edg e o f th e o v bi t 0 ov i n t n : o v co m p ara t or inte rrupt on nega tiv e g o i n g edge ena b le bi t 1 = th e o v if int e rrup t fl ag w ill be se t upon a nega tiv e g o in g e dge of t he ov 0 = n o ovi f in terru pt f l ag w i l l be s e t u pon a n e g a tiv e goi ng e d g e of the o v re gi ste r 6 - 5 : ov refcon: outp ut ov e r volt age de tect lev e l re giste r r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x oov7 oov6 o o v 5 oov4 o o v 3 o ov2 o ov1 o o v 0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 0 oo v < 7 : 0> : ou tpu t o v e r vol t ag e d e tec t le ve l c o nfig ura t ion bi t s v ov _ r e f ( v ) =2 * v bg * ( oov(de c )/2 55) http:///
MCP19114/5 ds20005281a-page 40 ? 2014 microchip technology inc. th e a/d co nve r ter c a l i b r ati on w o rd 8 c an be u s e d to i m p r ov e o v r e f acc u ra cy . an ad c m eas ure m e n t t a r- ge t ( t a r ge t i n e x am pl e 6 - 1 ) i s ob ta in ed by a d d i n g t h e a nal og mu x buf fer of fs et ( b u o ff set) to t he des ire d o v r e f vo lt a ge (ov r e f t a r g et) an d mu ltip ly ing th e re su lt by th e a d c ga in (g ad c ) . o v r e f is a d ju ste d u n til th e ad c re adi ng equ als or ex ce eds the t a rget . an ex am pl e o f o v r e f-c a li bra t io n fi rmw a re is as fo l- lo w s : ex amp l e 6- 1: ex amp l e ov re f correc t i o n routine //assumes th at calibration wor ds adccal and buff are read from //program me mory into variable s adcc and buoffse t, respectively. extern volat ile unsigned int a dres @ 0x01c; #define ovre ftarget (unsigned int) 0x0800 // ovref target = 2.0 v unsigned lon g tmp = (unsigned long)adcc*(ovrefta rget+buoffset); // adc reference + buffer offset unsigned int target = (unsigne d int)(tmp >> 15) - 3; // subtract adc t ypical offset erro r 3 unsigned int adc; ovrefcon = 0 x00; // clear ovrefcon adcon0 = 0 x09; // enable and set channel to ovref do { // adjust ovrefco n ovrefcon+ +; nop(); no p(); adc = 0; for (unsigned char i = 4; i > 0; i-- ) { adc on0bits.go_ndone = 1; whi le(adcon0bits.go_n done); adc += adres; } adc >>= 2; } while ((ad c < target) && (ov refcon != 0xff)); not e 1 : in thi s ex am ple , the l s b w e i ght o f o v r e ft ar g e t is se t t o 1/(2 10 ) v o l t . use r s ca n c h oo se t h ei r o w n re so lut i on dep end ing on th ei r a c c u ra cy requ ire m e n t. th e di git a l v a l ue o f 2.0 v i s determ i n e d a s fo llo w s : t r unc(2 . 0 x 2 10 ) = 204 8 (0 x08 0 0 hex ). http:///
? 2014 microchip technology inc. ds20005281a-page 41 mcp191 14/5 6. 3 d esat urat io n det ecti on for quasi -resona nt o p erat ion th e m c p191 1 4 /5 h a v e bee n de si gne d w i th a bui lt-i n de s a t u r a t i on de t e ct io n co mpar a t or mo d u l e c u st om m a d e fo r qu as i-reson ant top o l ogi es . th is is es pe cia l l y u s ef ul fo r led - ty pe a ppl ic ati ons . thr oug h the use of th e mc p1 91 14 /5, bo th sy nc hro nou s and a s y n c h ro nou s q uas i-re so nan t top o lo gie s c an b e im pl em ente d . th e d esa t c o m p ara t or m o d u le has th e s a me fea t ure s a s th e u v lo /o vlo and o v co mp ara t or m odu les , ex ce pt th at it i n c l ud es s o m e ad diti on al pro g ram m abl e p a ram e t e rs . th e d esa tc on re gis t er h o ld s th e se tup c o n t rol bit s f o r t h is mo du l e . c o mm on co n t ro l bi ts a r e t h e po la r i ty ed ge trig ger for t he i n te rrupt fla g < c d s i n tp > < c d s i n t n >, co mpar a t or o ut p ut po la r i ty c ont rol , o u tpu t ena ble < c d s o e > an d ou tpu t st a t us bit. as with th e oth e r c o m p ara t or m odu les , the c d s if i s ind e pe nd ent of th e c d s o e ena ble bit. o n th e fro n t en d co nne cte d to th e d esa t co mp arat or non -in v er ting inp u t, th ere is a tw o - ch ann el m u x tha t co nn ect s e i the r to t h e d esa t p pi n or to the fix e d i n tern al ly ge nera t ed ba nd ga p v o lt age . ad dition all y , th e i npu t o f fs et vol t ag e o f th e desa t co mp arato r is fa cto r y-trim me d to with in 1 m v ty pi ca lly . t hes e fa cto r y-tr im me d va lue s are sto r ed i n th e c a l w d 2 regi ste r at a d d r ess 20 81 h. fi rmw a re m u s t re ad th ese v a l ues i n to th e d s tc al reg i st er (1 96h ). i f m o re o f f s et i s de sire d, th e use r c a n a d ju st th e v a lu es w r itte n to t he d s tc al per t hei r im ple m e n t a tio n . regis t er 6-6: des a tcon: de satura t i o n comp ar ato r control regis t er r/ w- 0 r / w - 0 r / w- 0 r / w - 0 r / w- 0 r / w - 0 r / w- 0 r / w - 0 cdsmu x cdswde r eser ve d cdspol cds oe cds out c dsi n tp cdsi n tn bi t 7 bi t 0 le gen d: r = rea dabl e bi t w = w r i t ab l e b i t u = uni m pl emen te d bi t, rea d as ? 0 ? u = bi t i s unchan ged x = b i t i s u nkn own - n = v al ue a t por ?1 ? = b i t i s se t ? 0 ? = b i t is c l e a r e d bi t 7 cdsmux: d esa t co mp ar at or mo dul e mul t i p l e x e r c han nel s e l e ct i on bi t 1 = bg sel e c t e d 0 = desa t p sel e c t e d ( d ef au l t ) bi t 6 cdswde: de sa t co mp ar at or w a t c h dog en abl e bi t 1 = w a t c h dog s i g nal e nab l e s pwm re set 0 = w at c h dog s i g nal d oes no t al l ow pwm r es et bi t 5 r eser ved bi t 4 cdspol: desa t c omp ar at or pol ari t y sel ec t bi t 1 = desa t comp ar ato r ou tpu t i s i n ver t ed 0 = desa t comp ar ato r ou tpu t i s not i nv er t e d bi t 3 cdsoe: de sa t co mp ar at or ou tp ut en abl e bi t 1 = desa t comp ar ato r out pu t pwm i s e nabl ed 0 = desa t comp ar ato r out pu t pwm i s no t en abl ed bi t 2 cdsout : desa t comp a r at or outp ut s t at us bi t if c d spol = 1 (i nv er ted p o l a r i t y ) 1 = cdsv p < cds vn ( d es a t det e c t e d ) 0 = cdsv p > cds vn ( d es a t not det e ct ed ) if cdspol = 0 (non-inverted polarity) 1 = cdsv p > cds vn ( d es a t not det e ct ed ) 0 = cdsv p < cds vn ( d es a t det e c t e d ) bi t 1 cdsi n tp: cd sif co mp ar at or i n t e r r u p t on po si ti v e go i ng edge en abl e bi t 1 = th e cdsi f i n t e r r upt f l ag wi l l be s e t up on a pos i t i v e go i n g edge 0 = no cds if i n t e r r up t f l a g wi l l be set upon a p o si t i v e goi ng ed ge bi t 0 cdsi n tn: cd sif co mp ar at or i n t e r r u p t on ne gat i v e goi ng edg e enab l e b i t 1 = th e cdsi f i n t e r r upt f l ag wi l l be s e t up on a neg ati v e g o i ng ed ge 0 = no cds if i n t e r r up t f l a g wi l l be set upon a negative going edge http:///
MCP19114/5 ds20005281a-page 42 ? 2014 microchip technology inc. 6. 4 p r i m a ry inpu t c u rrent o f fse t adj u st pri m a r y inp u t cu rrent of fs et a d j u st pro v i des t he abi lit y to add of fse t to t he p r im ary inp u t c u rre nt s i gn al, thu s s e tti ng a pe ak pri m ar y c u rre nt li mi t. th is of fse t ad just i s c ont roll ed us ing the fou r bi t s in the ico a co n re gi ste r . regis t er 6-7: icoacon: inp u t curr en t offse t adj ust control re gis t e r u-0 u -0 u-0 u -0 r/w -x r /w -x r/w -x r /w -x ? ? ? ? i c o ac3 i coac2 i coac1 i coac0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 3- 0 ico ac<3 : 0 > : inp u t c u rre nt o f f s et adj us tm ent c onfi g u r atio n b i t s 0000 = 0 m v 0001 = 5 0 mv 0010 = 100 mv 0011 = 150 mv 0100 = 200 mv 0101 = 250 mv 0110 = 300 mv 0111 = 350 mv 1000 = 400 mv 1001 = 450 mv 1010 = 500 mv 1011 = 550 mv 1100 = 600 mv 1101 = 650 mv 1110 = 700 mv 1111 = 750 mv http:///
? 2014 microchip technology inc. ds20005281a-page 43 mcp191 14/5 6. 5 lead ing edge bl anki ng th e adj us t a b l e le adi ng edg e blan ki ng (leb) is u s e d to b l an k prim ary c u rre nt sp ik es res u l t ing fro m pri m a r y s w itc h tu rn-on. im pl em ent ing ad jus t ab le leb a llo w s th e sy ste m to ign o re tu rn-on no is e to bes t s u i t th e a ppl ic ation w i tho u t prim ary c u rre nt sen s e di sto r tio n fro m r c fil t eri ng. the r e a r e f our se ttin g s av ail a b l e for l eb, in cl udi ng ze ro. t hes e s ett ing s a r e c on t rol l ed vi a tw o bi t s in t he ic lebc o n reg i s t er . regis t er 6-8: icle bcon: inpu t curre nt lea d ing ed g e blank ing control regis t er u-0 u -0 u-0 u -0 u-0 u -0 r/w - x r /w -x ? ? ? ? ? ? i clebc1 i clebc0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1- 0 i c lebc<1 : 0 > : in pu t cu rren t le adi ng edge bla n k i ng c o n f igu r ati on bit s 00 = 0 n s 01 = 5 0 ns 10 = 1 0 0 n s 11 = 2 0 0 ns http:///
MCP19114/5 ds20005281a-page 44 ? 2014 microchip technology inc. 6. 6 s l ope compensat io n a ne gati v e v o l t ag e slo p e i s add ed to th e out put of th e e rror am pl ifi e r . th is i s d one t o pre v e n t su bha rm oni c i ns t abi li ty w h en: 1 . th e o pera t in g d u ty cy cl e i s grea ter t han 50 % 2 . w i de c ha nge s i n t he d uty c y c l e oc cur th e am oun t o f neg ati v e sl op e a d d ed to the e rror a m p lifi e r ou tpu t i s c ont roll ed by sl ope c o m p e n s a tio n s l e w rate c o ntro l b i t s . th e s l op e co mp en sat i on is e nab le d by cl eari ng th e sl p by b i t i n th e sl pcrcon re g i ste r . regis t er 6-9: slp crcon: s l op e co m p e n s a tion ram p control re giste r u-0 r / w -0 r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x ? slpby sl ps5 slps4 slps3 sl ps2 sl ps1 sl ps0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 6 slpby : slop e c o mp ens ati on byp ass c on t rol bi t 1 = sl ope co mp ens at ion is by p a s s e d 0 = sl ope compens at ion is no t by p a s s e d bi t 5- 0 slps<5 : 0>: sl op e c o m p e n s a ti on sl ew r a te c o ntrol bi t s slps (m v/s ) = 4 . 150 5 m v/s * e 0. 739 * ( de c ) http:///
? 2014 microchip technology inc. ds20005281a-page 45 mcp191 14/5 6. 7 m osfet dr iver pr ogramm abl e dead t i me th e turn -on de ad ti me o f b o th pd r v a nd sd r v l o w - si de d r iv e si gna ls c an be c o n f ig ured i n d epe nde ntl y to all o w dif f er ent m o sfet s and ci rcui t bo ard la yo ut s to b e us ed to c o n s tr uct a n op tim i z ed s y s t em (refe r to fi gu re 6- 1 ). cl eari ng the pdr vby a nd sdr vby bi t s in th e pe1 re gis t er e nab les the pd r v and s d r v low - s i d e dea d ti me rs respective l y . th e a m o unt of dea d t i m e a dde d i s c ont roll ed in the dead c o n re gi ste r . figure 6-1: mos f et dri ve r de ad ti m e pdt sdt pdrv sdrv regis t er 6-10: dea dcon: driv e r dead t i m e control re giste r r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x p d r v dt3 p dr vdt 2 pdr v dt1 p dr vdt 0 sdr v dt3 s dr vdt2 s d rvdt 1 s dr vdt 0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bit 7-4 pd r v d t < 3 : 0 > : pd r v d ead t i m e co nf igurat ion bit s (t td _1 ) 0000 = 16 ns delay 0001 = 32 ns delay 0010 = 48 ns delay 0011 = 64 ns delay 0100 = 80 ns delay 0101 = 96 ns delay 0110 = 1 1 2 n s delay 0111 = 128 ns delay 1000 = 144 ns delay 1001 = 160 ns delay 1010 = 176 ns delay 1011 = 192 ns delay 1100 = 208 ns delay 1101 = 224 ns delay 1110 = 240 ns delay 1111 = 256 ns delay bit 3-0 s d r v dt<3: 0 >: sd r v d ead t i m e co nf igurat ion bit s (t td _2 ) 0000 = 16 ns delay 0001 = 32 ns delay 0010 = 48 ns delay 0011 = 64 ns delay 0100 = 80 ns delay 0101 = 96 ns delay 0110 = 1 1 2 n s delay 0111 = 128 ns delay 1000 = 144 ns delay 1001 = 160 ns delay 1010 = 176 ns delay 1011 = 192 ns delay 1100 = 208 ns delay 1101 = 224 ns delay 1110 = 240 ns delay 1111 = 256 ns delay http:///
MCP19114/5 ds20005281a-page 46 ? 2014 microchip technology inc. 6. 8 o ut put regulat i on ref e rence v o l t age conf ig urat ion th e vrefcon re gi s t e r c o n t rol s the error am pl ifi e r re ferenc e vo lt a ge. th is refer enc e is us ed to s e t th e c u rre nt o r vo lt ag e re gul ati on s e t poi nt. vr ef c o n h old s t he d i gi t al v alu e us ed by an 8-bit l i ne ar d a c s e tti ng the ana log eq uiva l ent tha t ge t s s u m m ed w i th th e pe des t a l vo lt a ge (vzc ) a t the n on- inv e rti n g n ode of th e e rror am pli f ie r . vz c is eq ua l to th e b and ga p v o l t age (1.2 3v). the outp u t o f th e c u rren t s ens e am pl i f ie r a 2 i s al so r a i s ed o n t h e p e d e s ta l v o lta g e eff e c t iv el y c a n c e l in g i t s eff e c t o n t h e i n p u t . t h e p ede st a l is im pl em ent ed thro ugh out th e a nal og co ntro l l oop t o im prov e ac cu rac y at lo w l e v e ls . the vr ef d a c c an be adj us ted in 255 st ep s of 4.8 m v/ ste p . t o ens ure th e b e s t re gu lati on ac cu rac y w h il e i m p l em en tin g t he c u rre nt sens e amp l i f ier (a2 ) , th e i n it ial ga in error m u st be co ns ide r ed . an 8-b i t fa cto r y- sto r ed c al i bra t io n va lue a2c a l< 7:0> has bee n s t ore d in c a l w d 10 a t 20 8bh. t h is va lue ca n be use d to co mp ens ate for a2 gain err o r by ad jus t in g th e v re f c om m a nd. t o get the fi na l c om m and ed va lue , t he c a l w d 10 v alu e ge t s m ul t ip lie d by the orig ina l v re f de ci ma l co mm an d us in g th e v re f e x p r es si on re su lti ng i n a 1 6 -b it w o r d . rot a ti ng the 1 6 bit res u l t r i gh t p r odu ce s the fi na l c o m - pe ns ate d co mm an d in t he l eas t si gni fic a n t by te. th e m o s t s i gn ifi c an t b y te is un us ed. an ex am ple of the firm w a re is as fol l o w s : ex amp l e 6-2: ex amp l e a2 gain correcti o n regis t er 6-1 1 : v re fcon: curre nt/v olt a ge r e gulation s e t p o int control regis t er r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 vref7 v ref6 vref 5 v ref4 vref3 v ref 2 vref 1 v r e f0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 0 vref<7:0 >: v o lt a ge c ontr o ll ing c u rre nt r e gul ati on set p o in t bi t s vref (v) = v bg * ( vref(dec ) / 25 5) //assumes that calibration word a2cal has been read into variable a2comp unsigned int vref1_temp = vrefcon*a2comp; // a2 gain compensate for vrefcon vref1_temp >>= 7; vref1_temp &= 0x00ff; vrefcon = vref1_temp; http:///
? 2014 microchip technology inc. ds20005281a-page 47 mcp191 14/5 6. 9 v ref 2 v o l t age refer e nce th e vr ef2c o n reg i st er co ntro ls a s e c ond refer enc e d a c t hat ca n b e u s e d e x te rnal ly . for ex am ple , it ca n b e sent o f f c h ip a nd us ed to s e t th e cu rrent re gul ati on s e t poin t fo r a m c p163 1 pu ls e w i d t h m o d u l a tor . th e m c p19 1 1 4/5 m us t be c onf igu r ed in ma st er m od e w i th bit s m s c < 0:1 > = 01 i n t h e m o decon re g i ste r to c onn ec t v re f 2 to gpb 1. in s t a nd-al o ne mo de, v re f 2 is n o t a c c e s s i b le . v r e f c o n 2 ho ld s t h e di g i ta l va l u e us ed to se t th e vr ef 2 d a c . sinc e this re fere nc e i s i nten ded t o g o of f c hi p, the r e is no p ede st al of fs et as s o c i ate d w i th i t a nd it is referenc ed t o g n d . it is a n 8- bit l i n ear d a c an d ha s a rang e fro m 0v t o 1.2 3 v (bg ) eq ua ting to 255 s t ep s a t 4.8 m v/st ep. th e a/d co nve r ter c a l i b r ati on w o rd 8 c an be u s e d to i m p r ov e v re f 2 ac cura cy . an ad c m eas ure m e n t t a rg et (t arge t in ex am pl e 6 -3 ) is obt ain ed b y m u lt ipl y i ng th e d e si red v_{r ef 2} v o l t age (vr e f2 t a r g et ) by th e adc g a i n (adcc). v re f 2 is ad jus t e d u n til th e ad c re adi ng equ als or ex ce eds th e t a rget . an ex am pl e of v re f 2 -c o rrec tio n f i rm ware is a s fol l ows : ex amp l e 6- 3: vre f 2 c o rr ect i o n r o u t i n e reg i s t er 6- 12: vre f 2co n : v re f 2 v o l t ag e se t po int r e g i s t e r r/w - 0 r /w - 0 r/ w - 0 r /w - 0 r / w - 0 r / w -0 r/ w - 0 r / w -0 vref 27 vre f 26 v r ef2 5 vr ef24 vr ef2 3 vref2 2 v r ef2 1 v r ef2 0 bi t 7 bi t 0 leg e nd : r = r ea dab l e bi t w = wr i t abl e b i t u = u ni m pl em e nt ed b i t , r ea d as ? 0 ? u = bi t i s un ch ang ed x = bi t i s un kno w n - n = v a l ue at po r ?1 ? = b i t i s s e t ? 0 ? = bit is c l e a re d bi t 7 - 0 v r ef2 < 7: 0> : v o lt a g e co n t r o l lin g cu r r e n t re g u l a t io n s e t p o in t b i t s v re f2 (v) = v bg * ( vr ef 2( dec ) / 25 5) // assumes t hat the calibratio n word adccal has been read into va riable adcc extern volat ile unsigned int a dres @ 0x01c; #define vref 2t arget (unsigned int) 0x02cc // vref2 tar get = 0.7 v unsigned lon g tmp = (unsigned long)adcc*vref2tar get; // adc refer ence unsigned int target = (unsigned int)(tmp >> 15) - 3; // subtract adc typical offse t error 3 unsigned int adc; vref2con = 0 x 00; // clear vref2con adcon = 0x71 ; // enab le adc and set cha nnel to gpb1/vref2 do { // adjust vref2con vref2con++; nop(); nop( ); adc = 0; for (unsign ed char i = 4; i > 0; i--) { adcon0bits.go_ ndone = 1; while(adcon0bi ts.go_ndone); adc += adres; } adc >>= 2; } while ((adc < target) && (vref2con != 0xff )); note 1: i n t hi s ex ample , th e l s b weigh t of vref 2 t arg e t is s e t to 1/ (2 10 ) v o l t . us ers c a n c h o o se t h e i r o w n re s o lut i on dep endi ng on t heir a c cu rac y re quir e ment . th e d i git a l v a lue o f 0. 7v is det ermi ned as f o llows : trunc(0. 7 x 2 10 ) = 71 6 ( 0 x02cc hex ). ( 1 ) http:///
MCP19114/5 ds20005281a-page 48 ? 2014 microchip technology inc. 6. 10 anal og pe riph eral cont rol th e m c p19 1 1 4 /5 have v a ri ou s a nal og p e ri phe rals . th es e peri phe rals ca n be co nfi gure d to al low c u s t om iz abl e ope rati on. r e f e r to r egi ste r 6-1 3 for m o re in form ati on. 6 . 10 . 1 m o sf et ga te d r i ver e n abl e s th e m c p19 1 14/ 5 c an en abl e a nd/ or d i s abl e th e mos f e t ga t e d r i v e r o u t pu ts f o r t h e p r im ar y dr i v e (pd r v) and the se c o n dar y dri v e (sd r v) i nde pen den tly . set t in g t he bi t i n t he pe1 re gis t er ena ble s th e p r im ary driv e. se tti ng th e b i t in th e pe1 re gis t e r en ab les th e s e c ond ary dri v e . r e fe r to r egi ste r 6-1 3 fo r d eta il s. 6 . 10 . 2 m o sf et d r i ver de a d t i me a s de s c r i be d i n sec t ion 6 .7 ?m o s fet dr i ver pr og r a mm able d e ad t i me? , th e mo sfet d r iv e dea d ti me c a n be a d ju ste d . the d ead ti me c an be s e t i nde pen den tly for ea ch d r iv er from 16 ns to 256 ns i n i n c r em ent s of 1 6 ns us ing the d ead c o n regi ste r . d e ad t i m e c an als o be d i s abl ed for eac h d r iv er i nde pen den tly b y s e t t ing th e b y p a s s b i t s a nd < s dr vby> in t he pe1 re gis ter . 6.1 0 .3 se conda ry curre nt pos i tiv e se ns e p u ll -u p a hi gh-im ped anc e p u ll -up o n th e i sp pi n c an b e c onf igu r ed b y s e tti ng th e bit i n the pe1 re gis t er . whe n s e t, the i sp pi n is in tern al ly pul l ed -up to v dd . ref e r to r egi st er 6 - 13 fo r de tai l s . 6.1 0 .4 pw m s t e e rin g t h e m c p 1 9 1 1 4 / 5 h a v e ad di t i on al c o n t r o l c i r c ui t r y t o al lo w ope n-l oop rep o si tio n in g o f th e ou tpu t. th e pwm s tr _ pen b i t en abl es a p r im ary - onl y pwm si gna l of f i x ed fre que nc y an d duty cy cl e to re pos iti on th e ou tpu t v o l t ag e u p . the pw mstr _ sen b i t ena ble s a s e c ond ary-o n l y p w m sig n a l of fix e d freq uen cy an d du ty cy cl e to re pos it ion the o utp ut v o lt age dow n . whe n re pos iti oni ng out put v o l t ag e do w n , t he o u tp ut ov ervo l t ag e p r ote c ti on m u s t be a c ti ve al ong w i th pwm s tr_ sen f o r the pw m to p u ls e th e sdr v . fre q u enc y a nd duty c y c l e are c o n t rol l ed thro ugh tm r 2 re gis ters p r 2 a nd tm r 1l. pwm s tpr _ pen an d pwm s tr _ sen s hou ld ne ver be ac ti ve at the s a m e ti me , th ere f ore th e pw mst p r_pen i s the do mi na nt bi t. f o r q uas i-re so nan t op era t io n du rin g o p en -loo p re pos iti oni ng , th e d esa t c o m p ar ator ou tpu t s h o u ld b e di sa bl ed w i th th e < c d s o e > bit in the d e ad c o n re gis t er . regis t er 6-13: pe 1: ana l og p e ri ph e ral e nable 1 control re g i ste r r/ w -0 r /w -0 r/w -0 r / w -0 u-0 r /w -0 r/w -0 r /w - 0 pdr ven sdr ven pdr vby sdr vby ? i sp u e n p wm str_ pen pwm s tr_sen bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im ple m e n te d b i t, r ead as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a lu e a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 pdr ven: pdr v g a te d r ive ena b le bi t 1 = en a b led 0 = d i sabled bi t 6 sdr ven: sdr v g a te d r ive ena b le bi t 1 = en a b led 0 = d i sabled bi t 5 pdr v by : pd r v d e ad t i me by p a s s bit 1 = pd r v de ad tim e i s b y p a s s ed 0 = pd r v de ad tim e i s n o t b y p a s s e d bi t 4 sdr v by : sd r v d e ad t i me by p a s s bit 1 = sd r v de ad tim e i s b y p a s s ed 0 = sd r v de ad tim e i s n o t b y p a s s e d . bi t 3 u nim plem ente d: r e ad a s ? 0 ? bi t 2 ispuen: i sp w e ak pul l -u p en ab le b i t 1 = i sp w e a k p u ll -up is en abl ed 0 = i sp we ak pu l l - u p i s d i s a bl ed http:///
? 2014 microchip technology inc. ds20005281a-page 49 mcp191 14/5 6. 1 1 anal og bl ocks enable cont rol v ari ous a nal og ci rcu i t blo c k s ca n be en abl ed or d i s abl ed, a s sh ow n i n the abe c o n reg i s t er . th e abecon reg i s t er a l s o c o n t ain s bit s c ont roll in g an alo g an d di gi tal t e s t s i gn al s . t h es e s i g n a l s ca n be c onf igu r ed to g p a0. se ttin g th e b i t e n a b le s th e di git a l tes t si gna ls t o be c onn ect ed to g p a0. s e l e c t s the di git a l cha n n e ls . se tting en abl es the an al og tes t s i g nal s to b e c onn ec ted t o gp a0. if < a n a oen > a nd b o th g e t s e t, th e dig o e n b i t t a ke s pri o rit y . whe n an ao en i s n o t set , th e a nal og tes t s i gn al s a r e c onn ec ted to the int e rna l ad c . the ana log te st c h a nne l s e l e ct ion s a r e c ont roll ed throu g h the ad c o n 0 regi ste r . 6 . 1 1 . 1 m o sf et d r i ve r u n d e r v ol t a g e lo ck ou t se le ct io n th e m o sfet gate dri v e r s hav e i n te rnal un de r v ol t a g e p r ote c ti on tha t is c ont roll ed by th e b i t i n th e abeco n reg i s t er . si nc e t he ga te dri v e s upp ly i s pr o v i d ed ex te r n al l y th r o ug h t h e v dr p i n , th e driv ers a r e c a p abl e o f d r iv in g l o g i c le ve l f e t s o r h i gh er 10v (13 . 5v m a x i m u m ) fet s . de fau l t s to c l ea r , th ere f ore s e le cti ng a ga te dri v e u v lo of 2.7 v . se ttin g s e lec t s t he hi gh er 5.4 v g a te d r iv e uvlo. re fer to secti o n 4 .2 ? e le ctr i c a l c h ar ac ter i s t ics? for a ddi tio nal el ect r ic al spe c i f ic ati ons . 6.1 1 .2 er ror am pl ifier disa b l e th e erro r am pli f ie r c a n b e di sa ble d su ch t hat i t s o u tp ut is par k ed t o a k n ow n sta t e. t h e b i t d ef a ul ts t o z e ro an d the erro r a m p i s ena ble d duri ng no rma l op era t io n. i n c a s e the us er w a nt s to di sa ble the e rror am pl ifi e r , s e tt ing the ead is bit p a rk s t he e rror am pl ifi e r ou tpu t to jus t be low t he l o w c l am p v ol t age . u nd e r no rm al ope rati on, th e error am pl ifi e r o u tp ut run s be tw ee n 2 * bg (up per cl am p v a l ue) an d 1 * bg ? 1 5 0 m v (lo w er c l am p v a lu e). th e an alo g fe edb a c k c i rc uit r y u t il iz es an of f s e t pe des t al (1 * b g) to i m p r ov e a ccu r a cy a t lo w le v e l s . bi t 1 pwm s tr_pen: pdr v pwm s t ee ring bi t 1 = enables op en- loo p pw m c o n t rol to t he p d r v 0 = d i sa ble s ope n-loop pwm co ntrol to the pd r v bi t 0 pwm s tr_sen: sdr v pwm s t ee ring bi t 1 = enables op en- loo p pw m c o n t rol to t he s d r v 0 = d i sa ble s ope n-loop pwm co ntrol to the sd r v bi t regis t er 6-13: pe 1: ana l og p e ri phe ral e nable 1 control re g i ste r (continue d) regis t er 6-14: abe con: analog blo c k en able c o n t r o l r e gis t er r/ w -0 r /w -0 r/w -0 r / w -0 r/w -0 u -0 r/w -0 r /w - 0 digo en dsel2 d sel1 d sel0 druvsel ? eadis anaoen bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im ple m e n te d b i t, r ead as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a lu e at po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 digo en: dig t e st m u x to g p a0 co nne c ti on co ntro l 1 = d i g t e s t m u x ou tpu t is c onn ec ted to e x t e rna l p i n g p a0 0 = d i g t e s t m u x ou tpu t is no t c onn ec ted to ext e rnal pin gpa0 http:///
MCP19114/5 ds20005281a-page 50 ? 2014 microchip technology inc. bi t 6- 4 dsel<2 :0> 000 = qr s (ou t pu t of d esa t c o mp arato r ) 001 = pwm _l ( p wm out put af te r m ono st a b l e ) 010 = pwm (o sc ill ato r ou tput from th e m i c r o-c o n t rol l er ) 011 = tmr 2 eq (whe n t m r 2 equ als pr 2) 100 = ov (ov e r v ol t a g e c o m p ara t or outp u t) 101 = swfr q (sw i t c h i ng freq ue ncy o u tp ut) 110 = sd r v _o n _ o n esh o t (20 0 n s on e-s hot si gna l to res e t wd m log i c ) 111 = u n im pl em ente d bi t 3 druvsel : se lec t s ga te d r iv e u nde rvo l t a ge l o c k o u t l e v e l 1 = g a te dri v e uvlo s e t to 5.4 v 0 = g a te dri v e uvlo s e t to 2.7 v bi t 2 u nim plem ente d: re ad a s ? 0 ? bi t 1 eadis: erro r am pli f ie r dis abl e b i t 1 = d i sa ble s the er ror ampli f ie r (o utp u t p a rk ed low , cl am ped to 1 * bg ) 0 = e n a b l e s t h e er r o r am pl i f ie r ( n or m a l op e r at i o n ) bi t 0 anao en: anal og mu x o u t put c ontr o l b i t 1 = analog mu x outp u t i s c o n nec ted to ex tern al p i n gp a0 0 = anal og mu x outp u t i s n o t c o n nec ted to ex tern al p i n gp a0 regis t er 6-14: abe con: analog blo c k en able c o n t r o l r e gis t er (continue d) http:///
? 2014 microchip technology inc. ds20005281a-page 51 mcp191 14/5 6. 12 mode and rfb mu x contr o l t h e m o de con r e g i st er co nt r o l s t h e ma st e r / s l a ve c onf igu r ati on a nd th e in tern al re si sto r fee dba ck mu x fo r the cur r ent s e n s e am pli f ie r w h il e in qua si -res ona nt mo de . in ma ste r /sla ve m o d e , it a l l o ws th e v re f 2 si gna l of th e m as t er mc p1 91 15 de vi ce to be bu f f ered an d conn ec ted to a g p io pi n. thi s out put si gn al ca n b e c onn ec ted to a sl av e pwm dr ive r (m c p 16 31) at th e v re f in put to re gul ate c u rre nt vi a the sla v e pw m c o ntrol l e r . in s t a nd-a l o ne m o d e , th e v re f 2 un ity gai n b u f f e r i s n o t c o n nec ted to a se p a rat e g p io pin . th e r f b mu x s e l e c t s the out put of a2 cu rrent s ens e a m p lifi e r to b e co nne ct ed to th e in tern al 5 k ? fe edb ac k re s i s to r (qu a s i -res o n ant ) or t o th e i so u t pi n . regis t er 6-15: mode con: mas t er/s la v e an d rfb m u x c o ntr o l re gis t e r r/ w - 0 r /w -0 r/w - 0 u -0 u-0 u -0 u-0 u -0 msc1 msc0 rfb ? ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im ple m e n te d b i t, r ead as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a lu e at po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 msc < 1:0> : m a st er/sl a v e c o n f ig urat ion bi t s 00 = d e vi ce se t as s t an d-al on e un it 01 = de vi ce se t as m a s t e r 10 = de vi ce se t as s l a v e 11 = r e ser ved bi t 5 rfb<5 > : c u rre nt s ens e am pl ifi e r (a2 ) ou tpu t res i s t or feed ba ck mu x c o nfi gur atio n b i t 0 = r fb _i n t 5 k ? 1 = i so u t bi t 4- 0 unimplemented: read as ? 0 ? http:///
MCP19114/5 ds20005281a-page 52 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 53 mcp191 14/5 7.0 t y p i cal pe rform ance c urv es note : u n l e s s o t he rw ise in dic a t ed, v in =1 2 v , f sw = 1 5 0 kh z, t a =+ 2 5 c . f i g ure 7- 1: i q v s . t e mp er atu r e . f i g ure 7- 2: iq vs . t e m per atu r e in s l ee p mod e. f i g ure 7- 3: li ne r egul ati o n . f ig ure 7- 4: lo ad re gul ati on. f ig ure 7- 5: v dd dr opo ut v o l t age vs . o u tpu t cu r r en t (ma ) . f ig ure 7- 6: v dd dr opo ut v o l t age vs . t em per at ur e. note : th e grap hs an d t ab l es p r ov ide d fol l ow i ng thi s not e a r e a s t a t is tic al s um m ar y bas ed on a li mi ted nu mb er of s a m p le s an d a r e prov id ed fo r in form at ion a l pu rpos es o n ly . th e perf o rm ance ch arac te rist ic s lis ted h e rei n a r e no t tes t e d or g uara n te ed. in s o m e gra phs or t abl es , the da t a pr ese n te d m a y be o u t s id e the sp ec ifi e d o pera t in g ra nge (e.g ., o u t s id e s pec ifi ed pow e r su pp ly rang e) a nd ther efore , o u t s ide the w a rra nte d ra nge . 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 quiescent current (ma) temperature (c) v in = 32v v in = 25v v in = 12v v in = 6v non-s w itching 10 15 20 25 30 35 -40 -25 -10 5 20 35 50 65 80 95 1 1 0 125 sleep current (a) temperature (c) v in = 32v v in = 25v v in = 12v v in = 6v 5.04 5.05 5.06 5.07 5.08 5.09 5.10 6 8 10 12 14 16 18 20 22 24 26 28 30 32 v dd (v) v in (v) -40c + 1 25 c +25 c i dd = 1 ma 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.10 0246810 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 v dd voltage (v) current (ma) -40c +25c + 1 25 c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 02468 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 v dd dropout voltage (v) current (ma) -40c +25 c +125c 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 v dd dropout voltage (v) temperature (c) i dd = 20 ma http:///
MCP19114/5 ds20005281a-page 54 ? 2014 microchip technology inc. note : u n l e s s o t he rw ise in dic a t ed, v in =1 2 v , f sw = 1 5 0 kh z, t a =+ 2 5 c . f i g ure 7- 7: ou t p ut dr iv er d e a d t i me v s . cod e an d t e mpe r a t ur e. f i g ure 7- 8: so ur ci ng ou tpu t dr iv er r ds o n vs . t e mp er atur e. f i g ure 7- 9: si nk in g o u tput dr iv er r ds on vs . t e mp er atur e. f i g ure 7- 10: so ur ci ng o u tpu t dr iv er r ds on vs . t e mp er atur e. figure 7-1 1 : si nk in g ou tput dr iv er r ds on v s . t e mp er atu r e . f i g ure 7- 12: o s c i l l a t or f r equ enc y vs . t em per at ur e. 0 50 100 150 200 250 300 02468 1 0 1 2 1 4 16 pdrv/sdrv dead time (ns) code (d) -40c +25 c +125c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 r dson ( ? ) t e mperature (c) r pdrv-source r sdrv-source v dr = 10v 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 r dson ( ? ) t e mperature (c) r pdrv-sink r sdrv-sink v dr = 10v 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 r dson ( ? ) t e mperature (c) r pdrv-source r sdrv-source v dr = 5v 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 r dson ( ? ) t e mperature (c) r pdrv-sink r sdrv-sink v dr = 5v 7.92 7.94 7.96 7.98 8.00 8.02 8.04 8.06 8.08 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 oscillator frequency (mhz) t e mperature (c) http:///
? 2014 microchip technology inc. ds20005281a-page 55 mcp191 14/5 figure 7-13: normalized output demand vs. temperature. 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 -40 - 25 -10 5 20 35 50 65 80 95 1 1 0 125 normalized output demand t e mperature (c) output demand = 0.984v minimum maximum typical http:///
MCP19114/5 ds20005281a-page 56 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 57 mcp191 14/5 8 . 0 s ystem b e nc h t estin g t o a llo w for eas ie r sy st em des ig n a nd b en c h tes t in g, the m c p19 1 14/5 fe ature a mu lti p le xe r us ed to o u tp ut v a ri ous in terna l a nal og s i g nal s. t hes e s i g nal s c an b e m ea s ur ed on th e gp a0 pi n thro ugh a u ni t y ga in bu f f e r . th e co nfig ura t ion c o n t rol of the g p a0 p i n is f oun d i n th e abecon re gis t er . c o n t rol of the s i g nal s p r es ent a t th e ou tpu t of th e u n it y ga in ana lo g bu f f e r is fo und in the ad c o n 0 reg i s t er . . regis t er 8-1: adcon0 : an alo g -to- d i git a l c o ntr o l re gis t e r u-0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 ? chs4 ch s 3 chs2 chs1 c hs0 g o/ done adon bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bit 7 u n i m p l em en t ed : read as ? 0 ? bit 6-2 c h s<4:0>: analog channel select bit s 00000 = v in / n analog volt a ge m easurem ent (v in / 15 . 5328) 00001 = v re f + v z c (da c r e f e re nce v o lt age + v z c pedes t a l set t ing c u rrent reg u l a t i on lev e l ) 00010 = o v _ref ( r ef er ence f o r over volt age com p arat or) 00011 = v bg r (band gap r e f e renc e) 00100 = v s (vo l t age pr oport i onal t o v ou t ) 00101 = e a _s c ( e rror amplif ier af t e r slope com pensat i o n out put ) 00110 = a 2 ( secondar y c u rrent s ense amplif ier out put at r fb _ i n t connec t i on) 00111 = p e de st al (p edest a l v o lt age) 01000 = r es er v ed 01001 = r es er v ed 01010 = i p _a dj (i p af t e r p edest a l and o f f set adjus t (at pw m com p arat or)) 01011 = ip _ o ff_ re f ( i p of fs e t re fe r e n c e ) 01100 = v dr /n ( v dr / n a nal og driver voltage measu r ement = 0 . 2 2 9 v/ v * v dr ) 01101 = t e m p _s ns (analog volt a ge repr esent i n g int e r nal t e mperat ure) 01110 = dll _ vco n (delay locked loop v o l t age ref e re nce - c ont rol volt ag e f o r dea d t i m e ) 01111 = s l pcm p _re f (s l o pe com pensa t ion r e f e ren ce) 10000 = unim plement ed 10001 = unim plement ed 10010 = unim plement ed 10011 = unim plement ed 10100 = unim plement ed 10101 = unim plement ed 10110 = unim plement ed 10111 = unim plement ed 11000 = gp a 0 /a n0 (i. e . a ddr1) 11001 = gp a 1 /a n1 (i. e . a ddr0) 11010 = g p a2/ a n2 (i. e . t e mper at ure sens or i nput ) 11011 = gp a 3 /a n3 ( i . e . bi n ) 11100 = gpb 1 /a n4 11101 = gpb 4 /a n5 ( mc p191 1 5 on l y ) 11110 = gpb 5 /a n6 ( mc p191 1 5 on l y ) 11111 = gpb 6 /a n7 ( mc p191 1 5 on l y ) bit 1 go/ done : a/ d c onvers i on s t at us bit 1 = a / d conv ersion cyc le in pr ogress . set t i ng t h is bit st art s an a/ d conver sion c ycle. t h is bit is aut om at ically cleared by hardware when t he a/ d c onvers i o n has com p let ed. 0 = a / d conv ersion com p l e t ed/ not in prog ress bit 0 ad o n : a / d conve r sion s t at us bit 1 = a / d conv ert e r m odule is operat ing 0 = a / d conv ert e r is shut o f f and consum es no oper at ing current http:///
MCP19114/5 ds20005281a-page 58 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 59 mcp191 14/5 9.0 d e v ice calibration r e ad-only m e m o ry l o ca tio n s 20 80h th roug h 2 0 8 f h c ont ain fac t ory cal i b r ati on da t a . r e fer to se ction 1 7 . 0 ? f la sh progra m me mory c o ntrol? for in form at ion o n h o w to rea d fro m t hes e m e m o ry l o ca tio n s . 9. 1 c al ibr a ti on w o rd 1 th e d c s r f b<6 : 0> b i t s se t the o f fs et c a l i bra t io n for th e c u rre nt s ens e d i f f ere n ti al a m p lif ier (a2) w h e n c onf igu r ed us ing the int erna l fe edb ac k re si sto r . a c a l i bra t io n ran g e of 3 0 m v is pro v i ded w i th 20h an d 0 0h be in g mi ds cal e (no o f f s et ). the m sb is pol arit y o n ly . firm w a re m u s t rea d t hes e v a l ues a nd w r i t e the m i n to t he d c s c a l regi ste r to i m p l em en t of fs et c a l i bra t io n. regis t er 9-1: cal w d 1 : ca libration w o rd 1 re giste r u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? bit 13 bi t 8 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? dcsrfb6 dcsrf b 5 dcsrfb4 dcs rfb 3 dcsrfb2 dcsrf b 1 d c s r f b 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u nus ed bi t, rea d a s ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 7 u n used: r e ad as ? 0 ? bit 6-0 dcsrfb<6:0>: input differential current sense calibration bits when configured using internal feedback resistor http:///
MCP19114/5 ds20005281a-page 60 ? 2014 microchip technology inc. 9. 2 c al ibr a ti on w o rd 2 c a lib rati on w ord 2 is a t me mo ry loc at i on 2 081 h. it c ont ain s the c a li brat ion bi t s fo r th e d e s a tur a tio n c om p a r ator cu rren t m ea s ur em ent in put of fse t . fi rm w a re m u s t re ad the s e va lue s and w r it e th em in to th e d s tc al re gis t e r t o im pl eme n t th e fac t o r y of fs et c a l i bra t io n. th e fa cto r y o f f s et ca lib rati on w i ll mi nim i z e o f fs et v o l t ag e. th e de sat u rat i on com p arato r is one of th e few ex am ple s w h e r e the us er m a y w a n t to i m p l em en t thei r ow n of fs et vo lt a g e v a l ues. w r i t in g us er d e fin e d v a lu es t o the d s tc al re gis t er pr ovi d e s thi s fl ex ibi l i t y . thi s re gist er a l s o co nt a i ns the trim bit s n eed ed to t r im th e in tern al 5k fee dba ck re si sto r to w i thin 2 % us ing t he bit s . fir m w a re m u s t re ad th ese v a l ues and w r i t e the m in to the r f btc a l re gist er to i m p l em en t th e fa cto r y-t r im me d fe edb ac k r e si sto r va lu e. regis t er 9-2: cal w d 2 : ca libration w o rd 2 re giste r u-0 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 ? d st4 d st3 d st 2 d st 1 d st 0 bit 13 bi t 8 u-0 u -0 r/ p-1 r /p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? r fb t5 rfbt4 r f b t3 rfbt 2 r fbt 1 rf bt0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u nus ed bi t, rea d a s ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 un u s e d : r e ad as ? 0 ? bi t 12 - 8 ds t < 4 : 0 > : d e sat u rat i on c o m p ar ator c u rren t m eas ure o f fs et ca lib rati on bit s bi t 7- 6 un u s e d : r e ad as ? 0 ? bi t 5- 0 r f bt<5:0>: internal feedback resistor trim bits http:///
? 2014 microchip technology inc. ds20005281a-page 61 mcp191 14/5 9. 3 c al ibr a ti on w o rd 3 th e vr o <5:0> b i t s at m e m o ry loc a ti on 2 0 8 2h c a li bra t e th e o f fs et of t he b u f f er amp l i f ie r of t he outp u t vol t ag e re gul ati on refe renc e se t p o in t (v re f ) . fi rm wa re m u s t re ad thes e val u e s a nd w r ite the m to th e vr o c al re gis t er for p r op er c a li bra t io n. th e bg r < 3: 0> b i t s at m e m o ry loc a ti on 2 0 8 2h c a li bra t e th e ba nd g ap re ferenc e. fi rmw a r e mu st re ad t hes e v a l ues a n d w r i t e the m to th e bg r c a l regi ste r for p r ope r ca li brat ion . 9. 4 c al ibr a ti on w o rd 4 th e t t a< 3:0> bi t s a t m e m o ry loc a t i on 208 3h con t ai n th e c a l i bra t io n b i t s fo r the fa cto r y-s e t ov ertem p e r atu r e th res hol d. fir m w a re m u s t read th es e val u e s and w r i t e th em in to t he t t ac al reg i s t er f o r p r ope r ca li brat ion. regis t er 9-3: cal w d 3 : ca libration w o rd 3 re giste r r/ p-1 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 vro 5 vro4 vro3 vro 2 vro 1 vro 0 bit 13 bi t 8 u-0 u -0 u-0 u -0 r/p-1 r /p -1 r/ p-1 r / p -1 ? ? ? ? b g r 3 b gr 2 b gr 1 b g r 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u nus ed bi t, rea d a s ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 8 vr o< 5 : 0> : r e fe renc e v o l t ag e (v re f ) of fse t c ali brat ion bi t s bi t 7- 4 u n used: r e ad as ? 0 ? bi t 3- 0 bg r < 3 : 0 > : band g ap r e fere nc e c a li bra t io n bi t s regis t er 9-4: cal w d 4 : ca libration w o rd 4 re giste r u-0 u -0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? bit 13 bi t 8 u-0 u -0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? t t a 3 t ta 2 t ta 1 t t a 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u nus ed bi t, rea d a s ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 4 u n used: r e ad as ? 0 ? bi t 3- 0 ttacal<3:0>: overtemperature threshold calibration bits http:///
MCP19114/5 ds20005281a-page 62 ? 2014 microchip technology inc. 9. 5 c al ibr a ti on w o rd 5 th e t a n a < 9 :0 > b i t s at m e m o ry lo ca tio n 2 084 h con t ai n th e ad c re adi ng from th e in tern al tem pera t ure se ns or w h en the s i l i c on te mp eratu r e is a t 30c . th e te mp era t ure coe f f i ci en t of t he i n te rnal tem p e r atu r e s ens or is 16 mv/ c . 9. 6 c al ibr a ti on w o rd 6 th e fcal <6:0 > bi t s a t me mo ry lo ca tio n 208 5h s e t th e i n ter nal os c ill ato r c a li bra t ion . f i rm w a re mu st rea d th es e va lue s an d w r ite th em t o the o s c c a l reg i s t er fo r pro per ca lib rati on. regis t er 9-5: cal w d 5 : ca libration w o rd 5 re giste r u-0 u -0 u-0 u -0 r/ p-1 r / p -1 ? ? ? ? t ana9 t a n a 8 bit 13 bi t 8 r/p-1 r /p-1 r/ p-1 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 t a na7 t ana6 t a na5 t ana4 t a na3 t ana2 t a na1 t an a 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u nus ed bi t, rea d a s ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 8 un u s e d : r e ad as ? 0 ? bit 7-0 tana<9:0>: adc reading of internal silicon temperature at 30c calibration bits regis t er 9-6: cal w d 6 : ca libration w o rd 6 re giste r u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? bit 13 bi t 8 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? f cal 6 f c al 5 f cal 4 f c al 3 f cal 2 fcal 1 f c a l 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u nus ed bi t, rea d a s ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 7 un u s e d : r e ad as ? 0 ? bit 6-0 fcal<6:0>: internal oscillator calibration bits http:///
? 2014 microchip technology inc. ds20005281a-page 63 mcp191 14/5 9. 7 c al ibr a ti on w o rd 7 th e d c s <6 :0> b i t s at mem or y lo ca tio n 20 86h sto r e th e facto r y- set of fs et ca lib rati on fo r th e cur r ent s ens e d i f f e ren t ia l a m p lif ier (a2) w hen co nfi gur ed usi n g i so u t . a c onfi g u r ati on ran ge o f +/-30 m v i s pro v i ded w i th 20 h a nd 00h b e in g mi dsca l e (no of fse t ). the m sb i s pol arit y o n l y . fi rmwa re m u s t re a d th i s va l u e i n to th e dcscal re gis t er t o im pl em ent o f fs et c a l i bra t io n. if u s i ng th e i n ter nal fee dba ck res i s t or , refe r to r e gi s t e r 9- 1 . regis t er 9-7: cal w d 7 : ca libration w o rd 7 re giste r u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? bit 13 bi t 8 u-0 r/p-1 r/ p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? dcs6 d c s 5 dcs4 dcs3 d cs 2 d cs 1 dcs 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 7 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 6- 0 dcs<6:0>: differential current sense amplifier calibration bits when used with i sout . http:///
MCP19114/5 ds20005281a-page 64 ? 2014 microchip technology inc. 9. 8 c al ibr a ti on w o rd 8 th e ad c c al <13 : 0> bi t s at m e m o ry lo ca tio n 2 089 h c ont ain th e ca lib rati on bi t s for th e a/ d c onv erte r . ca l i b ra ti o n w o rd 8 (adccal <1 3 : 0 > ) co n t a i n s th e fa cto r y m e a s ure m e n t of t he full s c al e ad c r e ferenc e. th e va lu e repr ese n t s the n u m ber o f a/ d c o n v e r ter co u n t s p e r v o l t. adcc<4 : 0 > b i t s re p r e s e n t th e fra c ti o n o f an a/d c onv erter c oun t, w h i c h ca n p r ov ide add iti ona l p r ec isi o n w hen ov ers a m p li ng t he ad c f o r en ha nce d re so luti on . t h is c a l i b r ation w o rd c an be u s e d to c a l i bra t e sig n a l s rea d b y t he anal og -to-d i g i t a l co n v e r te r . regis t er 9-8: cal w d 8: ca libration w o rd 8 re giste r r/ p-1 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 a d cc1 3 a dcc1 2 a dcc1 1 a dcc1 0 a dc c9 adcc8 bit 13 bi t 8 u-0 r /p-1 r/ p-1 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 adcc7 adcc6 adcc 5 a dcc4 adcc3 adc c 2 a dc c1 adcc0 bi t 7 bi t 0 le gen d : r = read abl e b i t p = pro g ramm abl e b i t u = un im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 5 a dcc<1 3 :5 >: w h o l e n u m b e r of a / d co nv er t e r co un t 111111111 = 51 1 ? ? ? 000000000 = 0 bi t 4- 0 a dcc<4 : 0 > : frac ti on n u m ber of a/ d co nv erter co unt 11111 = 0 . 96 875 ? ? ? 00001 = 0 . 03 125 00000 = 0 . 00 000 http:///
? 2014 microchip technology inc. ds20005281a-page 65 mcp191 14/5 9. 9 c al ibr a ti on w o rd 9 c a lib rati on w o rd 9 is a t m e m o ry loc a ti on 20 8ah. th e v a l ue sto r ed at th is m e m o ry lo ca tio n repre s e n t s th e o f fs et vol t ag e (i n un it s of mv) of th e a nal og tes t bu f f e r . th is is an 8 - bi t, 2' s com pl em en t w ord t hat can be use d to compens ate an y s i gn al sen t th roug h th e ana l og tes t m ul t ipl ex er . see sec t i on 8 . 0 for te st si gna l d et a ils . regis t er 9-9: cal w d 9: ca libration w o rd 9 re giste r u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? bit 13 bi t 8 r/p-1 r /p-1 r/ p-1 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 buff7 buff6 buf f 5 b uff4 bu f f 3 b uff 2 buff 1 b uf f0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 8 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 7- 0 b u f f <7: 0 >: an al og bu f f e r o f f s et ca lib rati on bit s 11111111 = mi d s c a l e (-1 m v ) ? ? ? 10000000 = larg e s t ne gat iv e of fs et (- 128 mv) 01111111 = larg e s t po si tiv e o f fs et (127 m v ) ? ? ? 00000000 = mi d s c a l e (0 mv) http:///
MCP19114/5 ds20005281a-page 66 ? 2014 microchip technology inc. 9. 10 cal i br ati on w o rd 10 th e a2c a l < 7: 0> bi t s a t me mo ry lo ca tio n 208 bh c ont ain th e cal i b r ati on bit s for c u rren t se ns e am pl ifi e r (a2 ) gai n error . fo r b e s t r egu lat i on a c c u rac y us in g thi s a m p lifi e r , fi rmw a re c a n re ad thi s va lue a nd us e it to ad j u s t t h e v r e f co mma n d . se ction 6 .8 ?o u t put re gula t ion ref e renc e v o lt ag e confi gurati on? for d e t a ils . regis t er 9-10: cal w d 10 : calibration w o r d 10 regis t er u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? bit 13 bi t 8 r/p-1 r /p-1 r/ p-1 r /p-1 r/p-1 r /p -1 r/ p-1 r / p -1 a2cal 7 a2cal6 a2 cal5 a 2 cal4 a2 cal3 a2 c a l 2 a2 c a l1 a2 cal0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t p = pro g ram m abl e b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 13 - 8 u n i m pl e m en t e d: re a d a s ? 0 ? bit 7-0 a2cal<7:0>: current sense amplifier (a2) gain error calibration bits http:///
? 2014 microchip technology inc. ds20005281a-page 67 mcp191 14/5 1 0 .0 m e m o ry organization th ere are tw o t y pe s of m e m o ry in the m c p 191 14 /5: ? p ro gram m e m o ry ? d at a m e m o ry - s pe cia l f unc tio n r e gis t ers (sf r s ) - g en eral -purp o s e r a m 10. 1 p r ogram memory organi zat i on th e m c p 191 14 /5 ha ve a 13-b i t pro g ra m co un ter c ap abl e o f ad dre s s i ng an 80 00 x 1 4 p r ogra m me mo ry s p a c e. o n l y the fi rst 40 00 x 14 (0 000 h-0 fffh ) i s p h ys ic al ly im pl em en ted. add r es si ng a lo cat i on a bov e th is bo und ary w i l l cau s e a w r ap-ar ou nd w i thi n the firs t 4 000 x 14 s p a c e . th e r e set ve cto r is a t 00 00h an d th e i n ter r upt ve cto r i s a t 0 004 h (re fer to fig u re 10-1 ). th e w i d t h of t he prog ram m e m o ry bus (i ns truc tio n w o rd) i s 1 4 bi t s . si nc e al l in st ruct ion s a r e a s i ng le w o rd, th e m c p19 1 1 4 /5 have s p ace fo r 40 00 i n s t ruc t io ns . figure 10-1: p r o g ram m e m o ry m ap and st ack for m c p1 91 14 p c <12: 0> 13 00 00 h 00 04 h 00 05 h 0f ff h 1 fffh st ack l e v e l 1 st a c k l e v e l 8 r e se t v e cto r i n te rrupt v e c t or o n -c hi p pro g ra m me mo r y call, return retfie , retlw 100 0h 20 00 h 2 005 h 2 006 h 2 007 h 2 00a h 2 07f h 20f fh 20 03 h 2 004 h note 1: n o t co de p r ote c te d. shadows 00 0-f ffh 200 8h 20 80h 200bh 20 8fh 2090 h 2100 h 3 fffh use r ids ( 1 ) ic d in str u cti o n ( 1 ) m anu fac t ur ing c ode s ( 1 ) d e v i c e id (ha r dc ode d) ( 1 ) co n f i g w o rd ( 1 ) reserve d re se rve d fo r ma nu fac t uri ng & t e st ( 1 ) ca lib rati on w o rds ( 1 ) u nim pl em en ted s ha d ow s 20 00 - 2 0f f h http:///
MCP19114/5 ds20005281a-page 68 ? 2014 microchip technology inc. 10. 1.1 r ea ding p r ogram me mory as da t a th ere are tw o me thod s of a c c e s s i ng co nst ant s i n p r ogra m m e m o ry . the f i rs t m e t hod i s to us e t a b l es of retlw in st r u ct i o n s . t h e se co nd m e t h od i s t o s e t a fi le s s e le ct r egi ste r (f sr ) t o po int to the pro g ra m me mo r y . 10. 1.1.1 retlw i n st ru ct i o n th e r etlw in st ruc t ion c an be us ed to prov id e a c c es s to th e t a bl es of co nst ant s. the rec om m e nde d w a y to c r ea te s u c h t a bl es is sh ow n i n ex am pl e 1 0-1 . ex amp l e 10- 1: retlw ins t ruction th e brw i n st r u c t io n ma ke s t h i s t y pe of ta bl e v e r y s i m p le to i m p l em en t. if y our c o d e m u s t rem a in port abl e w i t h pr e v i o us ge n e r a t i o n s of mi c r o c on t r ol le r s , t h en t h e brw in stru ct ion i s not a v ai la ble, s o the o l de r t abl e-rea d me t h o d m u s t be us ed . 10. 2 d at a mem o r y or ganiza ti on th e da t a m e m o ry ( r efe r to fi gure 1 0 - 1 ) is p a r t iti o ne d i n to fou r b anks , w h ich c o n t ai n t he g ene ral purp os e r e g i s t ers (g pr ) an d th e s p e c i a l f u nc tio n r e gis t er s (sfr ). t he s p e c i a l fu nc tio n r egi st ers a r e lo ca ted i n th e fi rst 32 lo cat i on s of e a c h b ank . r e gis t er loc a ti on s 20 h-7 fh in ba nk 0, a0 h-efh i n ban k 1 a n d 1 20h -16f h i n ba nk 2 are ge ne ral purp ose r e g i s t ers , i m pl em en ted a s st atic r a m. al l oth er r a m i s un im pl em ente d a nd retu rns ?0? w h en read . th e r p <1 :0> bi t s in the st a t u s regi st er a r e th e b a n k se l e c t b i t s . ex amp l e 10-2: bank se lect t o m o v e v a l ues fro m one reg i s t er t o a noth e r r e gi ste r , th e va lu e mu st p as s th roug h th e w reg i s t er . thi s m ean s th at f o r al l reg i s ter-to -reg i s ter m o v e s , two i nst ruc t ion c y c l es ar e req ui r ed. th e entir e dat a m e m o ry c a n be a c c e s s e d e i th er d i r e ct l y or i n d i r e c t l y . di r e ct ad d r es si ng ma y r e qu i r e t h e us e of th e r p <1:0> bi t s . in dir e ct a d dre s s i n g requ ire s th e use o f t he fsr . ind i rec t add res s i n g us es th e in dire c t re gis t er po int e r (irp) bit i n the s t a t us r e g i st e r f o r ac ce ss t o t h e b a nk 0 / b a nk 1 o r t h e b a n k 2/ b a nk 3 a r ea s o f da ta m e m o r y . 1 0 . 2 . 1 g e n er al pu r p ose r e gi ste r fil e th e reg i s t er fi le i s org a n i ze d as 64 x 8 in th e mc p 1 9 1 14 / 5 . e a c h r e gi st e r i s a c c e s s e d , ei t h er di r e ct ly or in dire ctl y , th rou gh the fsr (re fer t o se ction 1 0 . 5 ? i ndi r e ct ad dress ing, indf an d fsr r e gis t ers? ). constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of co de? movlw data_index call constant s ;? the consta nt is in w rp1 r p0 00 - > b a nk 0 i s se l e c t ed 01 - > b a nk 1 i s se l e c t ed 10 - > b a nk 2 i s se l e c t ed 11 - > b a nk 3 i s se l e c t ed http:///
? 2014 microchip technology inc. ds20005281a-page 69 mcp191 14/5 10. 2.2 c o r e reg i s t ers th e c o re regi st ers co nt ai n th e re gis t er s th at d i rec t l y a f fe ct t he b asi c o pera t io n. th e c ore re gi ste r s c an b e addre s s e d f r om a n y b a n k . th es e regi st ers a r e li ste d b e lo w in ta b l e 1 0 - 1 . for d e t a ile d i n fo rm a t io n, re fer to t abl e 1 0-2 . 10. 2.2. 1 s t a t u s re gi ste r th e st a t u s reg i s t er con t ai ns : ? t he ar i t hm e t i c s t a t u s of t h e a l u ? t h e r e s e t st atus ? t h e b ank s e le ct bit s fo r da t a m e m o ry (r am ) th e st a t u s re gis t er c an be t he de sti n a t ion for an y in s t r u ct i o n, l i k e an y ot h e r r e g i st er . i f t h e s t a t u s re gis t er is the des ti nation for a n i n s t ruc t io n th at a f fe ct s th e z , d c o r c b i t s , th e w r i t e to thes e thre e b i t s i s di sa bl ed. th es e bit s are s e t or c l ea red ac co rdi n g to th e de vi ce lo gi c. furt herm o re , th e t o and pd bi t s are n o t w r it abl e. the r efo r e, the res u lt of an in stru ct ion w i th th e s t a t u s r e g i st er as d e s t i n a t io n ma y be di f f e r en t t h an i n ten ded . fo r ex am ple , clrf status w ill cl ear t he u ppe r thre e bi t s a nd s e t the z bi t. thi s le av es th e st a t u s reg i st er as ?000u u1uu? (whe re u = u n c h ang ed) . it i s rec o m m end ed, t here f ore , tha t onl y bcf, bsf, swapf a nd m ovwf ins t ru cti ons are us ed t o al ter th e st a tus register, because these instructions do not affect any status bits. table 10 -1: c ore registers add r e s s e s bankx x00h , x80h, x100h, o r x180h in d f x02h , x82h, x102h, o r x182h pcl x03h , x83h, x103h, o r x183h status x04h , x84h, x104h, o r x184h fsr x0ah , x8ah, x10ah, o r x18ah pclath x0bh , x8bh, x10bh, o r x18bh intco n note 1 : th e c and d c b i t s op era t e a s borrow and digit borrow ou t bi ts, respectively, in subtraction. regis t er 10-1: st a t us : st a t us regis t er r/w - 0 r / w -0 r/w -0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zd c ( 1 ) c ( 1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r x = bit is unk no w n ? 0 ? = bit is cl eare d ? 1? = bit is se t bi t 7 irp : r e g i st er ba nk sele ct bit (us e d for i ndi rec t ad dre s s i ng ) 1 = b ank 2 & 3 (1 00h - 1 ffh) 0 = b ank 0 & 1 (0 0h - ffh ) bi t 6- 5 r p <1 : 0 >: r e g i s t er ba nk sel e c t bi t s (us ed f o r d i r e ct ad dres si ng) 00 =ban k 0 (0 0h - 7fh ) 01 =ban k 1 (8 0h - ffh) 10 =ban k 2 (1 00h - 17 fh) 11 =ban k 3 (1 80h - 1f fh) bi t 4 to : t i m e -o ut bit 1 = a f t er pow e r-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred note 1: for borrow , th e p o larity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit in the source register. http:///
MCP19114/5 ds20005281a-page 70 ? 2014 microchip technology inc. 10. 2.3 s p e c i al function re giste r s th e s p e c i a l f unctio n r e g i s t ers are regi st ers use d b y th e c p u a nd pe rip hera l fun c ti ons for co ntro ll ing th e d e si red ope rati on o f the dev ic e (re fer t o fig u re 10 -2 ). th es e re gis t er s a r e s t at ic r a m. t h e s p e c ia l r e gi st e r s ca n b e cl a ssi f i ed i n to tw o se ts: c o re an d peri phe ral . t he s p ec ial fu nc tio n r e gis t e r s a s s o c i at ed w i th th e m i c r oc on trol ler co re are de sc ribe d i n t h is s e c t io n. t hose rela ted to th e o pera t io n o f th e p e rip her al fea t ure s are de sc ribe d in the a s s o c i ate d s e c t io n fo r tha t p e rip hera l f eatu r e. bi t 3 pd : pow e r- dow n bit 1 = a f t er pow e r-up or b y th e clr wdt in str u cti o n 0 = b y ex ec u t i o n o f t h e sleep in s t r u ct i o n bi t 2 z: ze ro b i t 1 = t he res u lt of a n a r ith m e t ic or l o g i c ope rati on is ze ro 0 = t he res u lt of a n a r ith m e t ic or l o g i c ope rati on is not ze ro bit 1 dc: digit carry/digit borrow bi t ( 1 ) ( a ddwf , ad dlw , sublw , subwf in st r u ct i o n s ) 1 = a ca rry-o ut f r om the 4 th l o w - o r der bit of t he re su lt o c c u rre d 0 = n o c a rry -out from th e 4 th low - o r de r bi t of the res u lt bit 0 c: carry/borrow bi t ( 1 ) ( addwf , addlw , sublw , subw f ins t ru cti ons ) ( 1 ) 1 = a ca rry-o ut f r om the m o st sig n ifi c a n t b i t of th e re su lt o c c u rre d 0 = no carry-out from the most significant bit of the result occurred regis t er 10-1: st a t us : st a t us regis t er (continu ed) note 1 : fo r bor r ow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit in the source register. http:///
? 2014 microchip technology inc. ds20005281a-page 71 mcp191 14/5 10. 3 dat a mem o ry figure 10-2: MCP19114/5 data memory map ind i rec t a ddr . ( 1 ) 00h ind i rec t a ddr . ( 1 ) 80h ind i rec t a ddr . ( 1 ) 100 h i n d ire c t add r . ( 1 ) 180 h tmr 0 01h opt i o n _r eg 81h tmr 0 101 h o ptio n _ r e g 181 h pc l 02h pc l 82h pc l 102 h p c l 182 h st a tu s 03h st a tus 83h st a t u s 103 h s t a tus 183 h f s r 04h fsr 84h fsr 104 h f sr 184 h po r t gp a 05h tr isg p a 85h w p u g p a 105 h i o c a 185 h po r tg p b 06h trisgp b 86h wpu g pb 106 h i o c b 186 h pir 1 07h pi e1 87h p e 1 107 h a n sel a 187 h pir 2 08h pi e2 88h m o d e c o n 108 h a n sel b 188 h pc on 09h 89h abecon 109h 189 h pc l a t h 0ah p c l a t h 8 ah pc la th 10ah p c l a t h 18ah in tc o n 0bh i n t c o n 8 bh in t c on 10bh i n t c o n 18bh tmr1l 0ch 8c h 10ch por t i c d ( 2 ) 18ch tmr1h 0dh 8dh 10dh trisi c d ( 2 ) 18d h t1 c o n 0eh 8eh 10eh ickbug ( 2 ) 18eh tmr2 0fh 8fh 10fh bigbug ( 2 ) 18f h t 2c o n 10h vin u v lo 90h ssp ad d 110h pm c o n 1 190 h pr2 1 1 h vinovlo 91h sspbuf 1 11h pm c o n2 191h 12h vincon 92h sspco n 1 112h pm adrl 192 h pwm p hl 13h cc1rl 93h sspco n2 113h pm adr h 193 h pwm p hh 14h cc1rh 94h sspco n3 114h pmd a tl 194 h pwm r l 15h cc2rl 95h sspm sk1 115h pm d a th 195 h pw m r h 16h cc2rh 96h sspstat 116h d s t c al 196 h 17h ccdcon 9 7 h ssp add2 1 1 7 h rfbt cal 1 97h 18h desa tcon 98h sspmsk2 118h o s ccal 1 9 8 h vrefcon 19h o vcon 99h 1 19h dcscal 199h v r ef 2con 1ah o vrefcon 9 ah 11ah t t a c al 19ah o s ct un e 1 bh deadcon 9bh 11bh bg rcal 1 9 b h adresl 1 c h s l p cr con 9ch 11ch vro c al 19ch adresh 1dh i coacon 9dh 11 d h 19d h adco n0 1 e h i cl ebcon 9 e h 11 e h 19eh adco n1 1 f h 9fh 11 f h r e s e rv ed 19f h g ene ral purp os e re g i ste r 9 6 by tes 20h g e neral purpo s e re g i st e r 80 byt e s a0h g ene ral pu rpos e re g i ste r 80 by t es 120 h 1a0h efh 16f 1ef 7fh acce s s e s bank 0 f0h ffh a cc e sse s ba nk 0 170 h 17f h a c ce sse s ba nk 0 1f0 h 1ffh ba nk 0 b ank 1 b an k2 ban k 3 u n im pl em ent ed dat a m e m o ry loc a t i on s, read as ' 0 '. note 1 : n o t a p h y s i c al reg i s t er . 2: on ly ac ce ss ib l e when dbgen = 0 and ickbug = 1 . fi le address fi le ad dres s fil e addre s s fi le ad dres s http:///
MCP19114/5 ds20005281a-page 72 ? 2014 microchip technology inc. t a ble 1 0 -2: m cp 191 1 4 /5 spe cial re giste r s sum m ary ban k 0 ad r n a m e b it 7 b it 6 b it 5 b it 4 b i t 3 b it 2 bit 1 b it 0 v alu e o n p or re set v a lu e o n a ll o t h e r r e s e t s ( 1 ) ba n k 0 00 h i n d f a ddr essi n g t h i s lo c a ti on us es co nte n t s of fs r to ad dre ss d a t a m e mo ry ( n o t a phys i cal r egi st er) xxxx xxxx xxxx xxxx 01 h t mr 0 t i m er0 mo du l e ? s re g i ster xxxx xxxx uuuu uuuu 0 2 h p cl p r o g r a m co u n te r ' s ( p c) l e a st sig n ifica n t b yt e 0000 0000 0000 0000 0 3 h s t a t u s i rp rp1 r p 0 t o pd zd c c 0001 1xxx 000q quuu 04 h f s r ind i re ct da t a me mo ry a ddr ess poi n t er xxxx xxxx uuuu uuuu 05 h p or t g p a gpa7 gpa6 gpa5 ? g pa 3 g pa 2 g p a 1 g pa 0 xxx- xxxx uuu- uuuu 0 6 h p o r tg pb gpb7 gpb6 gpb5 gpb4 ? ? gpb1 gpb0 xxxx --xx uuuu --uu 07h pir1 ? a dif bclif sspif cc2if cc1if tmr2if tmr1if -000 0000 -000 0000 08h pir2 cdsif ? ? otif ovif druvif ovloif uvloif 0--0 0000 0--0 0000 09h pcon ? ? ? ? ? ?por bor ---- --qq ---- --uu 0ah pclath ? ? ? w ri te buffer for up per 5 bi t s of p r og ra m co un ter ---0 0000 ---0 0000 0 b h i nt con g ie peie t 0 i e i nt e i o c e t 0 i f i nt f iocf ( 2 ) 0000 000x 0000 000u 0 c h t m r 1l h o l d i n g r e gi s t er f o r t h e le as t s i g n i f i c a n t b y te of t h e 1 6 - b i t t m r 1 xxxx xxxx uuuu uuuu 0d h t mr 1 h h o lding register for the most significant byte of the 16-bit tmr1 xxxx xxxx uuuu uuuu 0eh t1con ? ? t 1ckps1 t1ckps0 ? ? t mr 1 c s t mr 1 o n --00 --00 --uu --uu 0 f h t mr 2 t i mer2 module register 0000 0000 uuuu uuuu 10h t2con ? ? ? ? ? t m r 2 o n t 2 c kp s1 t2 ckps0 ---- -000 ---- -000 1 1 h p r 2 t i mer2 module period register 1111 1111 1111 1111 12h ? u n i m pl emented ? ? 13 h p w m p h l s la v e p h ase s h i f t r e g i ster xxxx xxxx uuuu uuuu 14 h p w m p h h s la v e p h ase s h i f t r e g i ster xxxx xxxx uuuu uuuu 15 h p w m r l p w m r e g i s t er lo w b y te xxxx xxxx uuuu uuuu 16 h p w m r h p wm register high byte xxxx xxxx uuuu uuuu 17h ? u n i m pl emented ? ? 18h ? u n i m pl emented ? ? 1 9 h v ref c o n vre f 7 v ref 6 vref5 v ref 4 v r e f 3 v ref2 vref1 v re f0 0000 0000 0000 0000 1 a h v ref 2 con v ref27 vref26 vref25 vref24 vref23 vref22 vref21 vref20 0000 0000 0000 0000 1bh osctune ? ? ? t un 4 t un3 t un2 t un1 t un0 ---0 0000 ---0 0000 1c h a d r e s l le ast s i gni fi ca nt 8 b i ts o f the a / d r e su l t xxxx xxxx uuuu uuuu 1 d h a dresh m o st sig nificant 2 bits of the a/d result 0000 00xx 0000 00uu 1eh adcon0 ? chs4 c hs3 chs2 chs1 chs0 go/done adon -000 0000 -000 0000 1fh adcon1 ? a dcs2 adcs1 adcs0 ? ? ? ? -000 ---- -000 ---- le gen d : ? = u ni m p l em en ted loc ati on s re ad as ?0? , u = un ch ang ed , x = un kn ow n, q = va lue de pen ds on con di t ion , s had ed = un i m pl em ente d note 1 : othe r (no n p o wer-u p) re s e t s inc l u de m c l r reset and watchdog timer reset during normal operation. 2: mclr a nd w d t re set doe s not af fec t the previous value data latch. the iocf bit will be cleared upon reset but will be set again if the mismatch exists. http:///
? 2014 microchip technology inc. ds20005281a-page 73 MCP19114/5 t a ble 1 0 -3: m cp 191 1 4 /5 spe cial re giste r s sum m ary ban k 1 ad d r nam e bit 7 b it 6 b it 5 b it 4 b it 3 b i t 2 bit 1 b it 0 v alu e o n p o r res e t v a l u es o n all o t h e r r e set s (1 ) b ank 1 80 h i n d f a d d r e ssi ng thi s l o cati o n u ses cont ents of fs r t o a ddr ess data m e m o r y (n ot a ph ysi cal r e g i ster ) xxxx xxxx uuuu uuuu 8 1 h o pti o n _ r eg rapu i n t e dg t0 cs t0 se psa ps2 ps1 ps 0 1111 1111 1111 1111 82 h p c l p r og ra m c o un ter' s (p c ) le ast s i g n i f i c a n t b y te 0000 0000 0000 0000 8 3 h s t a t u s i rp rp1 r p0 t o pd zd c c 0001 1xxx 000q quuu 84 h f s r in di re ct d a ta m e mo ry add re ss po i n te r xxxx xxxx uuuu uuuu 8 5 h t ri sg p a tri sa7 t r i s a6 t r i sa5 ? t ri sa3 tri sa2 tri sa1 t r i s a 0 1110 1111 1110 1111 8 6 h t ri sg pb tri sb7 t r i s b6 t r isb5 trisb4 ? ? t ri sb1 t r i s b 0 1111 0011 1111 0011 87 h pie1 ? a di e b cl i e sspi e cc2 i e cc1 i e tm r2 i e tm r1 i e -000 0000 -000 0000 88 h p ie 2 cdsie ? ? o ti e o vi e dru v i e o vl o i e u vl o i e 0--0 0000 0--0 0000 89 h ? un im plemented ? ? 8a h p c lath ? ? ? w r i te b u f f er f o r upp er 5 b i t s o f pr og ram co unt er ---0 0000 ---0 0000 8b h i nt con gie p e i e t 0ie i nt e ioce t 0i f i nt f iocf ( 2 ) 0000 000x 0000 000u 8c h ? un im plemented ? ? 8d h ? un im plemented ? ? 8e h ? un im plemented ? ? 8f h ? un im plemented ? ? 9 0 h vinuvlo ? ? u vl o 5 uv l o 4 u vl o 3 uvl o 2 u vl o 1 uvl o 0 --xx xxxx --uu uuuu 91 h v in ovlo ? ? o v l o5 ov lo 4 o v l o3 o v l o 2 o v l o1 ov lo 0 --xx xxxx --uu uuuu 92 h v inco n u v l oe n u v l oo ut uv lo int p uv loi n t n ov lo e n ov l oout o v l o i nt p o v l o i nt n 0x00 0x00 0u00 0u00 9 3 h cc1rl c a p t ur e1/ c o m p a r e1 r e g i ster 1 x low b y te ( l s b ) xxxx xxxx uuuu uuuu 9 4 h cc1rh c ap t ur e1 / c om p a r e1 r eg i s t er 2 x h i g h b y t e ( m s b ) xxxx xxxx uuuu uuuu 9 5 h cc2 rl c a p t ur e2/ c o m p a r e2 r e g i ster 1 x low b y te ( l s b ) xxxx xxxx uuuu uuuu 9 6 h cc2 rh c ap t ur e2 / c om p a r e2 reg i st er 2 x hi g h b yt e ( m s b ) xxxx xxxx uuuu uuuu 9 7 h ccdco n cc2 m < 3 : 0 > cc1 m < 3 : 0 > xxxx xxxx uuuu uuuu 9 8 h d esa t c on cdsm u x cdswde r e s e r ve d cdspol cdsoe cd s o ut cdsi n t p cdsi n t n 0000 0x00 0000 0u00 99 h o v c o n ? ? ? ? o ven o v o u t o vi ntp o vi ntn ---- 0x00 ---- 0u00 9a h ov r e f con o ov 7 oov 6 oov 5 oo v 4 o ov 3 o ov 2 o ov 1 oov 0 xxxx xxxx uuuu uuuu 9 b h d eadcon p dr v d t 3 pdr v dt 2 p dr vdt 1 pdr v dt 0 s dr vdt 3 sdr v dt 2 s dr vdt 1 sdr v dt 0 xxxx xxxx uuuu uuuu 9 ch s l p crco n ? s l pby sl ps5 sl p s4 s l ps 3 sl ps2 s l ps 1 sl ps0 -xxx xxxx -uuu uuuu 9d h i c o a c on ? ? ? ? i coac3 i co a c 2 i coac1 i coac0 ---- xxxx ---- uuuu 9e h i clebcon ? ? ? ? ? ? i cl ebc1 i cl ebc0 ---- --xx ---- --uu 9fh ? un im p l e m e nted ? ? le ge nd : ? = u n i m p l em ente d l o cati o n s r e a d a s ? 0 ? , u = u n cha n g ed, x = u n kn ow n, q = val u e de pen ds on c ond i t i o n , sha d e d = u ni m p l e m e n t ed no t e 1 : oth er (no n p o w e r-u p) res e t s include mclr reset and watchdog timer reset during normal operation. 2: mclr a n d wdt r e se t d o e s n o t a f fe c t th e p r e vio u s v a lu e d a t a la tch . t h e i o cf b i t will b e c l e a r e d u p o n r e se t b u t will b e se t a g a i n if t h e mi sm at c h ex i s t s . http:///
MCP19114/5 ds20005281a-page 74 ? 2014 microchip technology inc. t a ble 1 0 -4: m cp 191 1 4 /5 spe cial re giste r s sum m ary ban k 2 ad r n a m e b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 bit 1 b it 0 v a l u e o n p o r res e t v al u e o n al l o t h e r r e se t s ( 1 ) b ank 2 10 0h in d f a ddr essi n g th i s lo ca ti on use s co nte n t s of f s r to ad dre ss d a t a me mo ry ( n o t a phys i c a l re gi ste r ) xxxx xx xx xxxx xxxx 10 1h tm r 0 t i me r0 mo dul e ? s r e g i ster xxxx xx xx uuuu uuuu 10 2h p c l p r ogr am co u n te r's (p c ) l e a st si gn i f i cant byt e 0000 00 00 0000 0000 10 3h s t a t u s ir p r p 1 r p 0 t o pd zd c c 0001 1x xx 000q quuu 10 4h fs r i nd i r ec t da t a me mor y a ddr ess poi n t er xxxx xx xx uuuu uuuu 10 5h w p u gpa ? ? wpua5 ? w pua3 w p ua2 wpua1 wp u a 0 --1- 11 11 --u- uuuu 1 0 6 h wpug pb wp ub7 wpub6 wp u b 5 wpub4 ? ? w pub1 ? 1111 -- 1- uuuu --u- 1 0 7 h pe 1 p dr ven sdr ven pdrvby sdrvby ? i spue n pwm s t r _ p en pwm s t r _ sen 0000 -1 00 0000 -100 10 8h mo d e c o n m s c 1 msc0 rfb ? ? ? ? ? 001- -- -- 001- ---- 1 0 9 h ab eco n di goen d s e l 2 dsel 1 d sel 0 druvsel ? eadi s anao en 0000 0- 00 0000 0-00 10 a h p clath ? ? ? w r i te buf f e r for up per 5 b i t s o f p r og ra m co un ter ---0 00 00 ---0 0000 10 b h int c on gie p e i e t 0 i e i n t e ioce t 0if intf iocf ( 2 ) 0000 000x 0000 000u 10ch ? u n i m pl em en ted ? ? 10dh ? u n i m pl em en ted ? ? 10eh ? u n i m pl em en ted ? ? 10 fh ? u n i m pl em en ted ? ? 1 1 0 h ss p a dd add<7 : 0 > 0000 00 00 0000 0000 1 1 1 h s s p b u f s yn chr ono us s e ri al p o rt r e cei v e b u f f er/ t ra nsm i t r e gi ste r xxxx xx xx uuuu u uuu 1 1 2 h ss pco n 1 w co l sspo v sspen ckp s s p m < 3 : 0 > 0000 00 00 0000 0000 1 1 3 h ss pco n 2 g cen a cks t a t a c kdt a cken rcen pen rsen sen 0000 00 00 0000 0000 1 1 4 h ss pco n 3 a ckt i m p cie s cie b oen s daht sb cd e a hen dhen 0000 00 00 0000 0000 1 1 5 h ss pm sk1 m s k<7 : 0 > 1111 11 11 1111 1111 1 1 6 h ss pst a t sm p c ke d/ a ps r/w ua bf ?? 1 1 7 h ss p a dd2 a dd2 <7 :0 > 0000 00 00 0000 0000 1 1 8 h ss pm sk 2 m sk2 < 7 : 0 > 1111 1111 1111 1111 119h ? u n i m pl em en ted ? ? 11 a h ? u n i m pl em en ted ? ? 11 b h ? u n i m pl em en ted ? ? 11 c h ? u n i m pl em en ted ? ? 11 d h ? u n i m pl em en ted ? ? 11 e h ? u n i m pl em en ted ? ? 11 f h ? u n i m pl em en ted ? ? le gen d : ? = u n i m p l em ente d l o cati o n s r e a d a s ? 0 ? , u = u n cha n g ed, x = u n kn ow n, q = val u e de pen ds on c ond i t i o n , sha d e d = u ni m p l e m e n t ed no t e 1 : oth er (no n p o wer-up) resets include mclr reset and watchdog timer reset during normal operation. 2: mclr a n d wdt r e se t does not affect the previous value data latch. the iocf bit will be cleared upon reset but will be set again if the mismatch exists. http:///
? 2014 microchip technology inc. ds20005281a-page 75 MCP19114/5 t a ble 1 0 -5: m cp 191 1 4 /5 spe cial re giste r s sum m ary ban k 3 ad d r nam e bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 bit 1 b it 0 v al u e o n p o r r ese t v a l u e s o n all o t h e r r e s e t s ( 1 ) b ank 3 180 h i n d f a d dre ssi ng thi s lo ca ti on uses con t en t s o f f s r to add res s da t a mem o r y (n ot a p h ysi ca l re gi ste r ) xxxx xxxx uuuu uuuu 1 8 1 h o pti o n _ r e g rapu i n tedg t 0 cs t0 se psa ps2 ps1 ps0 1111 1111 1111 1111 182 h p c l p r o g ra m c oun ter ' s ( p c ) le ast s i g n i f i c a n t byte 0000 0000 0000 0000 1 8 3 h s t a t u s i rp rp1 r p 0 t o pd zd c c 0001 1xxx 000q quuu 184 h f s r i ndi r e ct data m e m o r y ad dre ss p o i n te r xxxx xxxx uuuu uuuu 185 h ioca ioca 7 ioca 6 ioca5 ? i o c a 3 ioca 2 ioca 1 ioca 0 000- 0000 0000 0000 186 h iocb iocb 7 iocb 6 iocb 5 iocb4 ? ? iocb 1 iocb 0 0000 -000 0000 -000 187 h a n s ela ? ? ? ? a nsa3 ansa2 ansa 1 a nsa0 ---- 1111 ---- 1111 188 h a n s elb ? ? a n s b5 ansb4 ? ansb2 ansb1 ? --11 -11- --11 -11- 189 h ? u n i mplemented ? ? 1 8 ah pclath ? ? ? w r i te buf f e r for up per 5 b i t s o f p r og ra m co un ter ---0 0000 ---0 0000 1 8 b h int c on gie p e ie t 0 ie int e i o ce t 0 if int f ioc f ( 2 ) 0000 000x 0000 000u 18ch po r t icd ( 3 ) in - cir cuit debug port register xxx --xx uuuu --uu 18dh tr i s icd ( 3 ) in - cir cuit debug tris register 1111 0011 1111 0011 18 e h i c kbug ( 3 ) i n - circuit debug register 0000 0000 000u uuuu 18fh b igb ug ( 3 ) in -c i rcuit debug breakpoint register 0000 0000 uuuu uuuu 190 h p mc o n 1 ? calsel ? ? ?w r e n w r r d -0-- -000 -0-- -000 191 h p mc o n 2 p ro gra m m e m o r y c o n t ro l r e g i ster 2 ( n o t a phys i cal r egi st er) ---- ---- ---- ---- 1 9 2 h p m a drl pm adrl 7 p m a drl 6 p m a drl 5 p m a drl 4 p m a drl 3 p m a drl 2 p m a drl 1 p m a drl 0 0000 0000 0000 0000 193 h p ma d r h ? ? ? ? p m a d rh3 p m adrh2 pm adrh1 p m adrh0 ---- -000 ---- -000 194 h p md a t l p md a t l 7 p m d a tl 6 p md a t l5 p m d a tl 4 p m d a t l3 p m d a tl 2 p m d a t l1 p m d a tl 0 0000 0000 0000 0000 195 h p md a t h ? ? p m d a t h5 pm d a t h 4 p m d a t h3 pm da t h 2 p m d a t h1 pm da t h 0 --00 0000 --00 0000 196 h d s t cal ? ? ? d st c a l 4 ds tcal 3 d st cal 2 dstcal 1 d st cal 0 ---x xxxx ---u uuuu 197 h r fb t cal ? ? r f b ca l 5 rf b c a l 4 r f b cal 3 rf bcal 2 r f b cal 1 rf b c al 0 --xx xxxx --uu uuuu 198 h o s c cal ? f c a lt 6 f c a lt 5 f c a lt 4 f c a lt 3 f c a lt 2 f c a lt 1 f c a lt 1 -xxx xxxx -uuu uuuu 1 9 9 h dcscal ? ? dcscal 5 dcscal 4 dcscal 3 dcsca l 2 dcscal 1 dcscal 0 --xx xxxx --uu uuuu 1 9 ah ttacal ? ? ? ? t ta 3 t t a 2 t ta 1 t ta 0 ---- xxxx ---- uuuu 1 9 bh bg rcal ? ? ? ? b gr t 3 b g r t 2 b gr t 1 b g r t 0 ---- xxxx ---- uuuu 1 9 c h vrocal ? ? ? v rot 4 v r o t 3 v rot 2 vrot 1 v rot 0 ---x xxxx ---u uuuu 19dh ? u n i mplemented ? ? 19 e h ? u n i mplemented ? ? 19fh ? re se r ved ? ? le ge nd : ? = u n i m p l em ente d l o cati o n s r e a d a s ? 0 ? , u = u n cha n g ed, x = u n kn ow n, q = val u e de pen ds on c ond i t i o n , sha d e d = u ni m p l e m e n t ed no t e 1 : other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: mclr a n d wdt r e se t d o e s n o t a f fe c t th e p r e vio u s v a lu e d a t a la tch . t h e i o cf b i t will b e c l e a r e d u p o n r e se t b u t will b e se t a g a i n if t h e mi sm at c h ex i s t s . 3: only acce ssible when db ge n = 0 and ickbug = 1 . http:///
MCP19114/5 ds20005281a-page 76 ? 2014 microchip technology inc. 10. 3.1 o pt io n_r e g re g i st e r th e o p tio n _r eg reg i s t er i s a read abl e an d w r it abl e re gis t er , w h ic h c o n t ai ns v a ri ous c ontro l b i t s to c onf igu r e: ? t i m e r 0/wd t pre s c a le r ? e x t ern a l gp a2/ i n t in terru pt ?t i m e r 0 ? w ea k p u ll -up s o n po r t g p a an d po r t gpb note : t o ac hie v e a 1:1 p r es cal e r as si gn me nt for t i mer 0 , a s s i g n th e pres ca ler to the wdt by s e tt ing psa b i t t o ?1? in the o p tio n _reg r egi ste r . r e fer to se ction 22. 1.3 ? s of tw a r e pr o g r a m m a- bl e pr es cal er ? . re gi ste r 1 0 - 2 : op ti on_ r e g : op ti on regi st er r/w - 1 r / w -1 r/w - 1 r / w -1 r/w - 1 r /w -1 r/w - 1 r /w -1 rapu intedg t 0 cs t0se psa ps 2 p s1 ps0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, read as ?0 ? -n = v a l ue a t po r x = bit is unk no w n ? 0 ? = bit is cl eare d ? 1? = bit is se t bi t 7 ra p u : port gpx pul l -up ena b le bi t ( 1 ) 1 = p o r t gp x p u l l - ups a r e d i s a bl ed 0 = p ort g p x pu ll-u p s are en abl ed bi t 6 intedg : int e rrup t edg e se lec t b i t 0 = i nte rrupt on ris i ng ed ge of in t pin 1 = i nte rrupt on fal lin g e dge of in t pi n bi t 5 t0c s : t m r 0 c l oc k sourc e s ele ct bit 1 = t rans iti on on t0c k i p i n 0 = i nte r nal in str u ct ion cycl e cl o c k bi t 4 t0se: t m r0 sou r c e edge sel e c t bi t 1 = i nc rement on hig h -to - low trans it ion on t0c k i pin 0 = in cre m e n t o n l o w-to- h ig h tra n s i ti on o n t 0 cki p i n bi t 3 psa: pres ca ler ass i g n m ent bit 1 = p res c al er i s ass i g ned to wd t 0 = p resc al er i s assi g ned to the t i m e r0 mo dul e bi t 2- 0 ps<2:0 > : pre s c a le r rate sel e c t bi t s note 1 : in divi d ual wpu x bi t m u s t al so be ena ble d . bit value tmr0 rate wdt rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1: 16 1 : 8 100 1: 32 1: 16 101 1: 64 1: 32 110 1: 128 1: 64 111 1: 256 1: 128 http:///
? 2014 microchip technology inc. ds20005281a-page 77 mcp191 14/5 10. 4 p cl and pcla th the p r ogr am c ount er (p c ) is 1 3-b its w i de. t he low byt e comes f r om the pc l r egist er , w h ich is a r eada ble a n d w r it abl e regist er . t he high byte ( p c < 12: 8>) is no t direct ly rea dable or w r itable and comes fro m p c la th . on any r ese t, t he pc is clear ed. fi gure 10-3 s h ow s t he tw o situat ions for load ing the pc : t he upper example show s how t he pc is l oaded on a w r it e t o pc l (p c l a t h <4:0 > ? pc h ) , w hile th e lo w er example in figu re 1 0 -3 show s how th e p c is loa ded d uring a cal l or go to inst r u cti o n (p cl a t h<4 : 3 > ? pc h) . figure 10-3: program counte r (pc) loading i n differ e nt s i tuations 10. 4.1 m o d if y i ng p c l re g i st e r ex ec uti ng a n y i n s t ruc t io n w i th t he pc l re gi ste r as th e d e st ina t io n s i m u l t ane ou sly c aus es th e pro g ra m c o unte r pc <12 : 8> b i t s (pc h ) to be rep l ac ed b y th e c ont ent s of th e pc la th regi ste r . th is a llo w s the e n ti re c ont ent s o f th e pr ogra m c o u n te r to be c h a nge d b y w r i t ing the des ire d up per 5 bit s to the pc la t h regi ste r . w hen th e l o w e r 8 bit s are w r it ten to the pc l reg i s t er , al l 1 3 bit s of the p r og ram c ou nter w i l l ch ang e to th e va lue s c ont ain e d in t he pc la th r egi ste r a nd th ose b e in g w r i tten to the pc l re gis t er . 10. 4.2 c o mp u t e d g oto a c o m put ed goto i s a c c om pli sh ed b y a ddi ng a n of fs et to th e pr ogra m cou n te r ( addwf pcl ). c a re sh oul d b e e x er cis ed w h en jum pi ng in to a loo k -u p t ab l e or pr o g r am b r a n c h ta bl e ( c om pu t e d goto ) by mo dif y in g th e pc l regi st er . ass u m i n g that pc l a th is s e t to th e t a bl e st a r t ad dres s, i f the t abl e le ngt h is g r ea ter tha n 2 55 in stru cti ons or i f t he lo w e r 8 b i t s o f th e me mo ry a ddre s s roll ov er from 0x ffh t o 0x0 0h in the m i d d le of th e t a b l e, th en pc l a th m u st b e inc r em en ted fo r eac h a ddre s s ro llo ve r tha t o c c u rs be tw ee n th e t abl e b egi nni ng and the t a ble lo cat i on w i th in the t ab l e. fo r mo re inf o rm ati on, re fer to app l i c at ion n o te an 55 6, ?im p l e m ent ing a t abl e r e a d ? (d s0 05 56). 10. 4.3 c omp u ted function ca lls a c o m p u t ed fun c ti on call a llo w s p r ogr am s to m a in t a i n t a ble s of fun c ti ons a nd pro v i d e ano the r w a y t o e x e c u t e s t ate m a c h i nes or loo k -u p t a b l e s . wh en pe rform i n g a t a ble read u s i ng a c o m put ed fu nc tion call , ca re s hou ld be exe r ci se d i f th e t a ble lo ca tion c r os ses a pc l m e m o ry bo und ary (ea c h 256 -by t e b l oc k ) . if u s i ng th e call i n s t r u ct i o n, t h e p c h < 2 : 0> a n d p c l re gis t ers are l oad ed w i th th e ope r an d of th e call in s t r u ct i o n. p c h < 6: 3 > i s l o ad ed wi th p c l a t h < 6: 3 >. 10. 4.4 s t a ck t h e m c p 1 91 1 4 / 5 ha ve an 8 - l e v e l x 1 3 - b i t w i de ha rdwa re s t a c k (refe r to f i gu re 1 0 -1 ) . t he s t ac k sp ac e i s n o t p a r t of ei the r pr ogram or d a t a s p ac e and th e s t a c k p oi n te r i s no t r ea d ab l e or w r i t ab l e. t h e p c is pu sh ed onto t he s t ac k w h e n call ins t ru cti on i s ex ec ute d or a n i n te rrupt c auses a bran ch . t he st a c k i s p o p e d in t h e ev en t o f a return , retlw or a retfie in s t r u ct i o n ex ec ut i o n. pc la th i s no t a f f e ct e d by a push o r pop op erati o n . th e st ac k op erat es a s a c i rc ula r buf fer . thi s m ean s th at af ter th e st a c k h a s b een pu sh e d ei ght ti me s, th e 9 th pu sh ove r w r ite s th e va lu e tha t w as s t ore d fro m th e firs t pu sh . th e ten t h p us h ov erw r i t es the se co nd p us h (an d so on ) . 10. 5 i ndir ect addres sing, i ndf an d fsr r e gist ers th e in d f regi ste r is no t a p h y s i c a l reg i s t er . addr ess i n g t h e i n d f r e g i s t e r w i ll ca us e i n di r e c t ad dr e s s i ng . in dire ct a d d r es sin g is po ss ib le b y us in g th e in d f re gist er . an y in st ruct ion u s i ng th e in d f reg i st er ac tu all y acce s s es dat a p o i n ted to by th e file se lect re g i ste r (fs r ). r e a d i n g indf i t se l f i n d i re ctl y wi l l pr odu ce 0 0h. w r it ing t o the in d f re gis t er d i rec t l y re sul t s in a no o pe r atio n (a lth oug h s t atu s b i t s ma y b e af fe cte d ). an e f fe cti v e 9 - bi t add res s is obt ain ed b y c onc ate n a t ing th e 8 - bi t fsr and th e i r p bi t in th e st a t u s reg i s t er , as sh ow n i n f i gu re 1 0 -4 . a s i m p l e p r og r a m t o c l e a r r a m l o c a t i on 40 h- 7 f h u s i n g i ndi rec t ad dres s i ng is sh ow n in exam pl e 1 0-3 . pc 12 8 7 0 5 pc l a t h < 4 : 0 > pc lath instruction with a l u re su lt got o, call opcode <1 0 : 0 > 8 pc 12 11 10 0 11 pcl a t h < 4 : 3 > pch pcl 87 2 pcl a th pch pc l de st in a t i o n note 1: there are no st atu s b i t s to in dic a te s t ac k ov er f l ow o r s t ac k u n de r f lo w co n d i t io n s . 2: th ere are no in stru cti o n s /m ne mo nics c a ll ed pu sh or pop . the s e a r e ac tion s t ha t o c c ur f r om t h e ex ec ut i o n of t h e call , return , retlw an d retfie i n s t r u ct i o ns o r t h e ve ct o r i n g t o a n in terr upt add res s . http:///
MCP19114/5 ds20005281a-page 78 ? 2014 microchip technology inc. ex amp l e 10-3: indir e ct ad dres s i n g figure 10-4: dire ct/indi rect a ddre ss ing movlw 0x40 ;initialize poi nter movwf fsr ;to ram next clrf indf ;clear indf reg ister incf fsr ;inc pointer btfss fsr,7 ;all done? goto next ;no clear next continue ;yes continue dat a memory i n d i rect ad d r essi n g di rect ad d r essi n g b ank select locat ion s e l e c t rp 1 rp 0 6 0 f r o m o pc ode i r p f il e selec t regist er 7 0 b ank select loca t ion s e lect 00 01 10 1 1 180h 1 ffh 00h 7f h b ank 0 b ank 1 b ank 2 b ank 3 for m e m o ry m a p de t a i l , re fer t o fi gur e 1 0 - 2 . http:///
? 2014 microchip technology inc. ds20005281a-page 79 mcp191 14/5 1 1 .0 de vice config u ratio n d e vic e c o nfi gura t io n co ns is t s o f c on f ig urati on w o rd, code pro t ec tio n a nd d e vi ce id . 1 1 . 1 conf igur ati on w o rd th ere are s e v e ra l c o nfi gura t io n w o rd b i t s th at all o w d i f f eren t tim ers to be ena ble d an d me mo ry pro t ec tio n o p tio n s . t hese are im ple m e n te d a s c o nfi gur atio n w o rd at 200 7h . no te : th e dbg e n bi t i n c o nf ig ur a t io n w o rd is ma na ge d a u t o mat i cal l y by de vi ce de ve lo pm en t t o o l s , i n c l u d i n g de bu gg er s an d pr o g r a mme rs . f o r n o r m a l de vi ce op er a t i o n , t h i s bi t sh ou l d be ma in tai n e d as a ' 1 ' . d e b u g is av ai la bl e on ly on t h e mcp 1 9 1 15 . regis t er 1 1 - 1 : c onfig: configuration w o rd r/ p-1 u -1 r/p-1 r /p -1 u-1 r/p-1 dbgen ?w r t 1 w r t 0 ?b o r e n bit 13 bi t 8 u-1 r /p-1 r/ p-1 r /p-1 r/p-1 u-1 u-1 u-1 ?cp mc l r e p wr te wdte ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13 dbgen : i c d debug bit 1 = i cd debug mode disabled 0 = i cd debug mode enabled bit 12 u n i m p l em en t ed : read as ? 0 ? bit 1 1 -10 w r t < 1:0>: f l ash p r ogram m e m o ry self w r it e enable bi t 11 = w rit e pro t ect i on off 10 = 000h t o 3f f h wr i t e prot ec t ed, 400 h t o f f f h may be modif i ed by p m co n1 cont rol 01 = 0 00h t o 7f f h wr i t e prot ec t ed, 800 h t o f f f h may be modif i ed by p m co n1 cont rol 00 = 0 00h t o f f f h writ e prot ect ed, ent i r e prog ram mem o ry is writ e prot ect e d . bit 9 u n i m p l em en t ed : read as ? 0 ? bit 8 bo re n : brow n-out reset enable b i t 1 = b o r dis abl ed during sleep and e nabled dur i ng operat ion 0 = b o r dis abl ed bit 7 u n i m p l em en t ed : read as ? 0 ? bit 6 cp : code prot ect i on 1 = p rogram m e m o ry i s not c ode pr ot ec t e d 0 = p rogram m e m o ry i s external read and write protected bit 5 mclre: mclr pin function select 1 =mclr pin is mclr f unct i on and weak internal pull-up is enabled 0 =mclr pin is alt e rna t e f unction, mclr function is internally disabled bit 4 pwrte : power - up t i m e r enable bit ( 1 ) 1 = p w r t disabled 0 = p w r t enabled bit 3 wd te: w a t c hdog t i m e r enable bi t 1 = w dt enabled 0 = w dt disabled bit 2-0 u n i m p l em en t e d : read as ? 0 ? note 1 : bi t is res e rv ed an d n ot controlled by user. http:///
MCP19114/5 ds20005281a-page 80 ? 2014 microchip technology inc. 1 1 . 2 code prot ecti o n c o de pro t ec tio n a l l o w s the d e v i ce t o b e prot ec ted fro m un a u t h or i z e d ac ce ss . i n t e r n al a cce s s t o t h e p r og r a m m e m o ry is un af fec t ed by an y c o d e pr otec ti on s e t t ing . 1 1 . 2 . 1 p r ogram me m o r y prote c ti on th e en tire p r ogram m e m o ry s p ac e is prot ect ed fro m e x te rnal re ads and w r it es by t he c p bit in th e c o nfiguration word. when cp = 0 , e x te rnal re ads an d w r i t es of pro gra m me mo ry are in hib i te d a nd a read w i l l re turn a ll ?0 ? s. the c p u ca n co nti nue to re ad pro g ra m m e m o ry , rega rdl e ss of the pro t ec tio n bi t s e tti ngs . w r iti n g the pro g ram m e m o ry i s d epe nde nt upo n th e wri t e pro t ec tio n se ttin g . refe r to s e ct i o n 1 1 . 3 ? w r i t e prote c tio n ? for m o re in form ati on. 1 1 . 3 w r it e p r ote c ti on w r ite prot ec tion all o w s t he de vi ce t o be p r ote c te d fro m u n in ten ded se lf-w ri tes . ap pli c a t ion s , su ch as bo ot l oad er s o f t w a re, c a n be p r ote c te d w h i l e a llo w i ng oth e r re gio n s of the prog ram m e m o ry to b e m o d i fi ed. th e wr t < 1:0 > bit s in th e c onf igu r ati on w o rd d e fin e t h e si ze of t h e pr o g r am m e m o r y bl o ck t h at i s pr o t ec t e d . 1 1 . 4 i d loca t i ons fo ur me mo ry loc ati on s (200 0h ? 2 0 03 h) a r e d esi gn ated a s id loc ati on s w here t he us er ca n sto re c hec k s u m or o t he r c o d e id ent ifi c at ion num be rs. t hes e l o c a tio n s are no t ac ce ss ib le d u ri ng n o rm al ex ec utio n b u t are read abl e an d w r it a b l e dur ing p r ogram /v erif y m o d e . o n ly the l e a s t si gni fic ant 7 bit s of t he id l o c a tio n s are re po rted w h en u s i ng m p lab i n teg r ate d d e vel o p m en t en vi ronm en t (id e ). http:///
? 2014 microchip technology inc. ds20005281a-page 81 mcp191 14/5 1 2 .0 os cillat o r mo des th e mc p1 91 14/ 5 h av e one os ci ll ator co nfi gur atio n w h i c h i s a n 8 m h z i n te r n al os ci ll a t or . 12.1 i nter nal osci ll ator ( i nt osc) th e int e rna l o s c ill ato r m o d u l e prov id es a s y s t e m c l o c k s o u r ce of 8 m h z . the fr equ enc y of th e int e rna l os ci l l a t or c a n b e t r im me d w i t h a ca li b r at i o n v a l u e i n t h e osctune re g i ste r . 12. 2 o sci ll ator cal i br ati o n th e 8 m h z int e rna l o s c i l l at or i s fac t or y-c a li bra t ed. th e fa cto r y ca li br ati o n v a lu es r e sid e in the r e ad- o nl y c a l w d 6 r e g is t er . t h es e v a l u es mu st b e r e a d f r om t h e c a l w d 6 regi st er a nd s t or ed i n th e o s c c a l r e gi ste r . re f e r to s e ct i o n 1 7 . 0 ? f l a sh p r o g r am me mo r y con t r o l? f o r th e pro c e dur e on read in g th e pro g ram me mo r y . 12. 3 fr e quency t uning in user mode in add iti on to the fac t ory ca lib rati on, the b a s e fre que nc y c an be t une d in the us er' s a ppl ic ati o n. thi s fre que nc y tuni ng ca p a b i l i ty al low s th e u s er to dev i a t e fro m the fac t or y-c a li bra t ed freq uen cy . th e u s er ca n tu ne th e fre que nc y by w r iti ng to the o s c t u n e re gis t er (refe r to r e gi ste r 12 -1 ). note : th e fc al <6:0 > bi t s i n th e c a l w d 6 re gis t er m u s t b e w r itt en in to the o s c c a l re gis t er to c a l i bra t e t he inte rna l os c ill ato r . regis t er 12-1: osctune : osci l l ator t uni ng regis t er u-0 u-0 u -0 r/ w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ? ? ? t un4 tun3 t un2 t un1 tun0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7- 5 u n i m pl e m en t e d: rea d as ? 0 ? bi t 4- 0 tun<4 :0 > : fre qu enc y t uni ng b i t s 01111 = ma xi mu m f r eq u e n cy 01110 = ? ? ? 00001 = 00000 = c e nte r freq ue ncy . o s c ill ato r m odu le is runn in g at the ca lib rate d fr equ enc y . 11111 = ? ? ? 10000 = mi ni mu m f r eq u e n c y http:///
MCP19114/5 ds20005281a-page 82 ? 2014 microchip technology inc. 12. 3.1 o scil la t o r del a y up on p o we r - u p , w a ke -u p an d ba se freque ncy cha nge in a ppl ic ati ons w h ere th e osc t u n e reg i s t er is u s e d to s h i f t t he freq ue ncy of the in tern al os ci lla tor , th e a ppl ic ati on sh oul d not ex pe ct th e f r equ en cy o f th e i nter nal os cil l a t or to st a bil iz e im m edi ate l y . in thi s c as e, th e frequ en cy m a y s h if t gra d u a ll y tow a rd th e new v al ue. the ti me fo r t his f r equ enc y sh if t is l es s tha n eig ht c y c l e s o f th e base fre que ncy . o n po w e r-up , the dev ic e is hel d in re se t by th e p o w e r-u p ti me if the pow e r-up tim e r i s ena ble d . fo ll ow in g a w a k e -u p from slee p m ode or po r , a n i n ter nal d e la y of ~ 1 0 s is in vo ke d to al low th e me mo ry b i as to st abi liz e b efo re p r ogra m ex ecu t io n c an beg in. t a ble 1 2 -1: s um mar y of re giste r s ass o ciated wi t h clock s o ur ces nam e bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 re gis t e r on pag e osctune ? ? ? t un4 tun3 t u n 2 t u n 1 t u n 0 81 le gen d : ? = u n i m p l em en t e d l o c a t i on s, r e ad a s ? 0 ?. sh ade d c el l s are not us ed by cl ock s our ces . t a ble 1 2 -2: s um mar y of configuration w o rd as soci ate d w i th clock s o urce s name bit s bit -/7 b it -/6 b it 13 /5 bit 12 /4 bit 1 1 /3 bit 10/2 b i t 9/1 b it 8/0 re gis t e r on pa ge co nfig 6 13 :8 ? ? ? ? ? ? ? ? 62 7:0 ? f cal 6 fcal 5 f cal 4 fcal 3 f cal 2 fcal 1 f cal 0 le gen d : ? = u n i m p l em en t ed locations, read as ? 0 ?. shaded cells are not used by clock sources. http:///
? 2014 microchip technology inc. ds20005281a-page 83 mcp191 14/5 13 . 0 re se t s th e res e t log i c i s us ed to pl ac e the m c p191 1 4 /5 in to a k now n st ate . th e s ourc e of th e re se t c an b e d e ter m i ned by us ing th e de vi ce st atus b i t s . t h e r e a r e m u l t ip l e w a ys to r e s e t t h es e d e v i ce s: ? p ow e r - o n r e se t (p o r ) ? overtemperature reset (ot) ?mclr re se t ?w d t r e s e t ? b ro wn-ou t res e t (bo r ) to a l l o w v dd to s t ab ili ze , a n o p ti ona l p o wer-u p tim e r c an be ena ble d to ex ten d th e r e se t tim e af te r a po r ev e nt . so me re gi ste r s a r e no t af fec t ed i n a n y r e se t co ndi t io n; th eir s t at us i s un kn ow n on por a nd un ch ang ed i n an y ot her r e s e t. m o s t o t her reg i s t ers a r e res e t to a ?r es et s t ate ? on : ? p ow er - o n r e se t ?m c l r re se t ?mclr r e s e t duri n g slee p ? w dt re se t ? b ro wn-ou t res e t wd t (w atc hdo g t i m e r) w a k e -u p do es n o t ca us e re gis t er res e t s in th e s a m e man n e r as a wd t r e se t, since wake-up is viewed as the resumption of normal operation. to and pd bi t s are s e t or cle a re d d i f f ere n tl y i n di f f e r en t r e s e t s i tu ati ons , a s i ndi ca ted in ta b l e 1 3 - 1 . th e s o f t w a re ca n u s e th ese bi t s to de term ine th e na ture of the res e t. refe r to ta b l e 1 3 - 2 fo r a ful l de sc rip t io n o f r e s e t s t a t es of all reg i s t ers . a si mp lif ied b l oc k di agra m of th e on -c hip r e se t c i rcu i t is sh ow n i n fig u re 13- 1 . the mclr r es et p a t h ha s a noi se fi lte r t o d ete ct an d ignore sm a ll pul se s. r efer to secti on 5 .0 ? d igit al ele c tr ic al c h ar a c ter i stics ? fo r pul s e -wid th s pec if ica t io ns . figure 13-1: s i mpli f i ed b l ock di agram o f o n -chi p re s e t cir cuit wdt module v dd rise detect brown-out reset sleep boren mclr/test_en pin v dd external reset s rq on-chip rc osc 11-bit r ipple c ounter pwrt enable pwrt chip_reset power-on reset time-out reset brown-out reset t abl e 1 3 - 1 : t im e- o u t in v a rio u s si t u ations power-up w a k e -up from sl eep pw rte = 0 pw rte = 1 t pw r t ?? http:///
MCP19114/5 ds20005281a-page 84 ? 2014 microchip technology inc. 13. 1 p ower- on reset (por) th e on- chi p po r c i rc uit ho lds the c h ip i n r e se t unti l v dd ha s reac he d a hi gh en oug h l e v e l for prop er o pera t io n. t o t ak e a dva nt a ge o f the por , s i m pl y c onn ec t the m c lr pin th rou gh a res i s t or to v dd . thi s w i ll e lim in ate ex terna l r c c o m pon ent s us ua lly ne ede d to cr eate pow e r-on r e se t. w hen the dev ic e s t art s n o rm al o pera t io n (e xit s th e r e set c ond iti on) , d e v i c e ope rati ng p a r am ete r s (i.e ., v o l t age , freq uen cy , te mp erat ure, e t c.) m u s t b e me t to en s u r e proper operation. if these conditions are not met, the device must be held in reset until the operat- ing conditions are met. 13.2 mclr m c p191 1 4/5 have a noise filter in the mclr re se t p ath. the fil t er w ill de tec t an d i gno re s m a l l pul se s. it sh ou ld be no ted tha t a w d t r e s et do es no t d r iv e mcl r pi n l o w . v o lt a ges app li ed to t he m c lr p i n t h at e x ce ed i t s s pec if ica t io n can result in both mclr re s e t s a n d ex c es s iv e c urre nt b ey ond the dev ic e s pec if ica t io n du rin g the esd event. for th is reas on , m i c r oc hi p re com m end s th at the m c lr p i n n o l on g er be t i ed di rec t ly t o v dd . the us e of a r e si st or-c ap ac ito r (r c ) ne tw ork , a s s h o w n in fi gure 1 3 - 2 , i s s u g ges te d. an i n te rnal mc l r opti on i s e nab led by c l e a ri ng th e m c lr e b i t in th e c o n f ig r egi ste r . whe n m c lr e = 0 , th e r e set si gna l t o th e c h ip is ge ne rated in tern all y . wh en m c lr e = 1 , the m c lr p i n be co me s a n ex te r n al res e t i n p u t. in thi s mode, the mclr pin has a weak pull-up to v dd . figure 13-2: recommended mclr circuit t a ble 1 3 -2: s t a tus/p con bit s and the i r s i gnifican ce po r bor to pd con d itio n 0x11 po we r-o n re s e t u011 brow n - out r e s e t uu0u wdt rese t uu00 wdt w a k e -up uuuu mclr r e s e t d u ri ng norm a l op erati o n uu10 mclr reset during sleep legend: u = unchanged, x = unknown note : the por c i rc uit doe s n o t p r odu ce an i nter nal r e se t w hen v dd de c l i n e s . t o re -ena ble the po r , v dd mu st r e ac h v ss (a gn d ) f o r a m i nim u m o f 10 0 s . v dd mclr r 1 1k ? (or greater) c 1 0. 1 f (o ptio nal , n o t c r iti c a l ) r 2 10 0 ? (needed with sw 1 (optional) m c p191 14 /5 c apa ci t o r ) http:///
? 2014 microchip technology inc. ds20005281a-page 85 mcp191 14/5 13. 3 b ro w n - out reset ( b o r ) th e bo r e n b i t <8 > in th e c o n f ig re gis t er e nab les or d i s abl es t he bo r m ode, as def ine d in the c o n f ig re gis ter . a b r ow n-o u t o c c u rs w h e n v dd fal l s bel ow v bo r for g r ea ter th an 100 s m i n i m u m . o n a n y r e s e t (po w er-on , bro w n-ou t, w a tc hdo g t i me r , e t c . ), th e chi p w i ll rem a i n in r e s e t u n ti l v dd r i se s ab ov e v bo r (re fer to f i gu re 1 3 -3 ). if en ab led , t he pow e r - up t i m e r w i l l b e i n v o ke d by the r e set an d w i ll k eep th e c h i p i n r e se t a n a ddi tio nal 64 ms . figure 13-3: brow n - o ut s i tuations note : th e pow e r-up t i me r is e nab le d by the pwr t e b i t in the co nfig re gis t er . if v dd dr op s be low v bo r w h il e th e powe r-up t i mer is r unn ing , t he ch ip w il l go ba ck i n to a brow n- out r e s e t a nd the pow e r-up timer w ill be re-i nit i al iz ed. on ce the v dd ri ses ab ove v bo r , th e power- up t i m e r wi ll ex ec ute a 64 m s res e t. v dd inte rnal re s e t v dd v dd int e rna l re se t inte rna l re se t v bo r v bo r v bo r 64 ms ( 1 ) 64 ms ( 1 ) 64 m s ( 1 ) <6 4m s note 1 : 64 ms delay only if pwrte bit is programmed to ? 0 ?. http:///
MCP19114/5 ds20005281a-page 86 ? 2014 microchip technology inc. 13. 4 p ower- up t i m e r (pwr t) th e pow e r-up t i m e r p r ov ide s a fi xed 6 4 m s (n om ina l ) ti me -ou t o n po wer-up o n l y , from p o r res e t. th e po wer-up t i m e r ope rate s f r om an int e rna l rc o s c ill ato r . th e ch ip i s k ept in r es et a s l ong as p w r t i s a c ti ve . the pwr t de lay al lows th e v dd to ri se to a n a c c ept abl e l e v e l. a bi t (p wrte ) i n th e config re gis t er ca n d i s abl e ( i f s e t) or ena ble (i f c l ea red or pr o g r am me d) t h e p o w e r - u p t i me r . th e po w e r-up t i m e r del ay w ill v a ry from c h ip to chi p d ue t o: ?v dd va r i at i o n ? t em per ature v a ria t io n ? p r o ce ss va r i a t ion the pow e r- up t i mer opt ionally delays device execut ion af ter a por event. th is timer is typically u s e d to allow v dd to s t abilize bef ore all o w i ng the device t o st ar t runnin g . th e pow e r-u p t i m e r is c ontr o ll ed by th e pwr t e bi t i n th e c o n f ig re gis t er . 13. 5 w at chdog t i m e r ( w d t) r e set th e w a tc hdo g t i me r g ene rate s a r e set if the fi rmw a re d oe s no t i s s u e a clrwdt in str uct ion w i t hin th e tim e-o ut p e r i od . the t o an d p d bits in th e s t a t u s re gist er ar e chan ged to ind i cat e t he w d t r eset . r e fe r t o se ction 1 6 . 0 ? w at chdo g t i me r (wd t )? for m o re in f o r m a t i o n. 13. 6 s t a rt -up sequence u p o n th e rel eas e o f a po r , th e fol l o w i n g mus t o c c u r be fore th e de vi ce beg ins e x e c ut ing : ? p o w e r-up t i m e r ru ns to c o m p leti on (if en a b le d) ? o sc il lat o r s t art - up tim e r ru ns to com p l e ti on ?m c l r m u s t be rel eas ed (if enabled) the total time-out will vary based on pwrte bit s t atus. for ex ample , w i th pwr t e bit e r as ed (pwr t dis abled), there w ill be no t i me-out at a ll. fi gures 13-4 , 13-5 and 13 - 6 d epict time - o u t sequenc es. since the tim e-out s occur f r om the p or pulse , if m c lr is kep t low l ong en ough, the time - o u t s w ill expire. then, bringing mclr high w i ll b egin executi on im medi ately ( r ef er t o figure 13-5 ). thi s is useful for tes t ing purpos es or t o sy nchroniz e m o r e than one mc p 1 91 14 / 5 dev ice operatin g in p a rallel. 13. 6.1 p ow er control (pcon) re g i ste r th e po w e r c o ntro l (pc o n ) re gis t er ( a d d res s 8eh) ha s two s t a t us bit s to i ndi ca te wha t typ e of re set o c c u rre d la s t . figure 13-4: t i m e -out s e que nce o n power-up (delayed mclr ): case 1 note: vo lt a ge s p ik es bel ow v ss at th e mc l r p i n, in duc in g cu rrent s grea ter th an 80 ma, m a y ca us e la tc h-up . th us, a s e ri es re si sto r of 50 -100 ? s ho uld be us ed w h en a ppl yi ng a ?low? l ev el to th e mc l r pi n , ra the r tha n pull ing thi s pin di rec t ly to v ss . t pw r t t ios cst v dd mclr internal po r pwr t t i m e -o ut os t t i m e - o ut i n ter nal r e s e t http:///
? 2014 microchip technology inc. ds20005281a-page 87 mcp191 14/5 figure 13-5: time-out seque nce on power-up (delayed mclr ): case 2 figure 13-6: time-out sequ ence on power-up (mclr wi th v dd ) 13. 7 d et ermini ng the cause of a rese t u p on an y r e s e t, m u lt ipl e bit s in th e st a t u s an d pc o n regi ste r are u pda ted t o ind i c a te t he c aus e of th e r e s e t. t a bl es 13 - 3 an d 13 - 4 s how th e r e s e t conditions of these registers. v dd mclr in tern al po r pwr t t i m e -o ut os t t i m e - o ut internal reset t pw r t t ioscst v dd mclr inte rna l po r pwr t t i m e -ou t ost t i me -o ut internal reset t pw r t t i o sc st t able 1 3 -3: reset status bits and their significance po r bor to pd cond ition 0x 1 1 p o we r-o n re se t u0 1 1 b r ow n-o ut r e se t uu 0 u wd t re se t uu 0 0 wd t w a k e - u p fr o m s l ee p uu 1 0 i n te rrupt w a k e -up fro m sl e e p uu u u mcl r re se t du rin g no rma l op er a t io n uu 1 0 mcl r re se t du rin g sle e p 0u 0 x n ot allowed. to is s e t o n po r . 0u x 0 n ot allowed. pd is se t on po r . http:///
MCP19114/5 ds20005281a-page 88 ? 2014 microchip technology inc. t a ble 1 3 -4: r es e t condition for s p ec ial re g i s t er s ( note 2 ) condit i on pr o g ram coun ter st a t us r e g i ster pcon r e g i ster po w e r-on re s e t 000 0h 00 01 1xxx -- -- --0u bro w n-ou t r e s e t 0 0 0 0 00 01 1xxx -- -- --u0 mcl r r e s e t dur ing no rma l op era t ion 000 0h 00 0u uuuu -- -- --uu mcl r r e s e t dur ing sle e p 000 0h 00 01 0uuu -- -- --uu w d t r es et 000 0h 00 00 uuuu -- -- --uu w d t w a k e -u p fro m slee p p c + 1 uu u0 0uuu -- -- --uu in terru pt w a ke -up from sl eep pc + 1 ( 1 ) uu u1 0uuu -- -- --uu le gen d : u = u n c h ang ed, x = unk no w n , - = uni mp l e m e n t ed bi t , r e a d s as ? 0 ?. note 1 : w hen the wa k e -up is du e to an in terru pt a nd gl oba l en abl e b i t ( g ie) is se t, th e re turn ad dres s is pus he d o n th e s t ac k and pc is lo ad ed w i th t he in te rrup t ve ct or (0 004 h) a f ter ex ecu t io n o f pc + 1. 2: if a s t a t us bit is no t im pl em ent ed, tha t bi t w i l l b e re ad a s ? 0 ?. http:///
? 2014 microchip technology inc. ds20005281a-page 89 mcp191 14/5 13. 8 p ower cont rol ( p c o n) regi ster th e po w e r c o ntro l (pc o n ) re gis t er co nt a i ns fl ag bit s to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) th e pc o n re gis t er bit s a r e s h o w n in r e gi s t e r 13 - 1 . reg i s t er 13- 1: pco n : po we r control re giste r u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ?por bor bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7- 2 u n i m pl e m en t e d: rea d as ' 0 ' bit 1 por : p o w e r-o n r e s e t s t atus b i t 1 = n o powe r-on res e t o c c u rre d 0 = a power- on re s e t oc c u rred (m u s t be s e t in s o f t ware af ter a powe r-on r e s e t oc c u rs ) bi t 0 u n i m pl e m en t e d: rea d as ' 0 ' t able 1 3 -5: s um mar y of re giste r s ass o ciated wi t h res e t s nam e bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 re gi s te r on pa ge pcon ? ? ? ? ? ?por bor 89 status ipr rp1 rp0 to pd zd c c 69 le gen d : ? = un im ple m e n te d bi t, re ad as ? 0 ?. s h ad e d c e l l s ar e no t us ed b y r e se t s . note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. http:///
MCP19114/5 ds20005281a-page 90 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 91 mcp191 14/5 1 4 .0 inte r rupt s th e m c p19 1 14/5 ha ve mu lti p le so urc e s of inte rrup t : ? e xt e r na l i n t e r r u pt ( i n t p i n) ? i n t erru pt-o n- c h ang e (i oc ) inte rrupt s ? t im er 0 ov er f l ow i n te r r u pt ? t im er 1 ov er f l ow i n te r r u pt ? t i m e r 2 m a tc h i n ter r upt ? a dc in terru pt ? s y s t e m inp u t u n derv o l t ag e erro r ? s ys te m i n pu t ove r vo l t ag e e r r o r ? ssp ?b c l ? d es at urat ion d e te cti o n ? g ate d r iv e u v l o ? c ap ture /c om p a r e 1 ? c ap ture /c om p a r e 2 ? o v e rtem pe ratu re th e i n terr upt c ontro l (i n t c o n ) regi ste r an d th e pe riph era l in terru pt re que s t (pirx ) re gi s t e r s re c o rd i ndi vi dua l in terru pt r equ est s i n fl ag b i t s . th e in t c o n re gis t er a l s o has ind i v i du al a nd gl oba l in terru pt en abl e bi ts. th e gl ob al int e rrup t enab le bi t, gi e, i n the in t c o n re gis t er , en abl es (if s e t ) all un ma sk ed inte rrup t s, or d i s abl es (i f c l e a red ) all i n te rrupt s. in div i d ual i n te rrupt s c an be dis a b l ed th rou gh the i r co rres p o ndi ng en abl e b i t s i n the in tc o n re gi ste r a nd piex re gis t ers . gi e i s cl ea r e d o n r e se t . wh e n an i n t e r r u p t is se r v ic ed , t h e f o ll ow in g ac ti o n s oc cu r au t o m a ti ca l l y : ? t h e g i e i s cl eare d to di sa ble any fu rthe r in terru pt ? t h e re turn ad dres s is pus he d o n to the st ack ? t h e pc i s loa ded w i th 00 04h th e fi rm wa re with in th e in terru pt serv ic e rou tin e (isr) s hou ld de term in e t he so urc e o f th e int e rrup t b y pol lin g th e i n terr upt f l ag bi t s . the interrupt fla g b i t s mu st b e cl ea r e d be f o r e e x it i n g t h e i s r t o av o i d r e pe a t ed i n ter r upt s. bec aus e the g i e b i t is c l ea red , a n y in terru pt th at oc cu rs w h il e ex ec utin g the isr w i l l b e rec o rde d th rou gh it s i n ter r upt fla g but w i l l n o t ca use th e p r oc ess o r to re dir e ct to t he interrupt v e ct or . th e retfie i n s t ruc t io n e x i t s the is r by p opp ing th e pr evi o u s add res s from th e st a c k , r e st orin g the sa ve d c ont ext fro m the s had ow re gist e r s and s e tti ng the g i e bi t. fo r add iti ona l in form ati o n o n a s p e c i f ic inte rrup t ? s op era t io n, re fer t o i t s p e ri phe ral ch apte r . 14. 1 i nter rupt lat e ncy fo r ex ternal int e rrupt ev en t s , su ch as the in t p i n or po r t g p x ch ang e in terru pt, t he i n terr upt l a te nc y w i l l be t h ree o r f our in st ruct ion c y c l e s . th e ex ac t l a te nc y de pe nds up on w h en the inte rrup t ev en t oc cu rs (re fer to fi gur e 1 4 - 2 ). t he l a te nc y i s th e s a m e for one- or tw o - cy cl e i n st r u c t io ns. 14. 2 g p a 2 / i n t i n ter r upt th e e x te rna l i n te rrupt on the g p a 2 /int pin i s ed ge -trig gere d , e i th er o n th e ri si ng e d g e , i f th e in ted g bi t i n th e o p ti on _ r eg regi ste r i s s e t, or the fal lin g ed ge , if the in ted g bi t is c l ea r . w hen a v a l i d edg e ap pe ars on th e gp a2/ i n t p i n, th e i n tf bit in th e in tc o n re gi ste r is s e t. thi s int e rrupt c a n be di sa ble d by cl eari n g th e in te c ont rol bi t in th e in tc o n r e gi ste r . th e i n tf b i t mu st be cl eare d b y so f t w a re in th e in terru pt se rvi c e r o uti ne befo r e re -ena bli n g thi s i n terr upt. t he g p a2 /in t in terru pt ca n w a k e up th e p r o c es so r f r om s l ee p, if t h e in te b i t w a s s e t p r i o r t o go in g into slee p. r e fe r t o secti on 1 5.0 ? p ow er-d ow n m ode (sle ep)? for de t a i l s on sl ee p a n d se ction 1 5 . 1 ? w ake -up from slee p? fo r tim i ng of w a k e -u p from sl eep thro ugh g p a2 /int i n te rrup t . note 1 : in div i d ual int e rrup t fla g bi t s are s e t, re gard l es s of the st atu s o f th eir c o rre spo n d i ng ma sk bi t o r the g i e bi t. 2: w hen an i n s t ruc t io n th at c l e a rs the gie b i t is ex ec ute d , an y in terru pt s tha t w e re p end ing for ex ec utio n i n t he n ex t c y c l e a r e i gno red. the in terru pt s w h i c h w e re i gno red are s t il l pe ndi ng to be s e rv ic ed w h e n t he g i e bit is se t ag ain . note: the ansel register must be initializ ed to c onf igu r e an an alo g c ha nne l as a di git al in pu t. pin s c o nf igu r ed a s an al og i n pu t s wi l l re a d ?0? and ca nno t gen erat e an in terr upt. http:///
MCP19114/5 ds20005281a-page 92 ? 2014 microchip technology inc. figure 14-1: inte rrup t l ogic figure 14-2: int p i n inte rrup t t i m i ng tmr1if tmr1ie s spi f ss pi e io c f ioce intf in t e gi e pe ie w a ke-up (i f in s l ee p m ode) interrupt to cpu peif adif adie cds i f cd s i e oti f ot i e ov if ov ie druvif druvie bc li f bc l i e tmr2f tmr2e t0if t0ie plx2 uv loi f uv l o i e ovloif ovloie plx1 cc2i f cc2i e cc1i f cc1i e intcon q2 q 1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 cl kin int p i n intf fla g (intcon re g . ) gi e bit (intcon re g . ) instructi o n f l ow pc ins t ru cti o n fe tch e d instruction executed pc pc + 1 pc + 1 0 004 h 00 0 5h in st (0 00 4h) in st (0 00 5h) du m m y cy cl e ins t (pc) in st ( p c + 1 ) in st (p c ? 1 ) ins t (00 04h ) du m m y cy cl e in st (pc) ? no te 1: i n t f f l ag i s sa mpled h e re ( e very q 1 ). 2: as ynchr onous int e r r upt lat ency = 3 - 4 t cy . s ynchr onous lat enc y = 3 t cy , w here t cy = i n st r uct i on c ycle t i m e . lat ency is t he sam e whet her i n s t (pc) is a s i ngle-c ycle or a t w o-cy cle inst ruc t ion. 3: clk o u t is av ail able only i n i n t o sc and rc o s cil l at or modes . 4: f o r m i nimum wid t h of i n t pulse , ref e r t o a c s pecif icat ions i n s e c t io n 5 .0 ?dig it al e le c t r ic al ch a r a c te r i sti c s ? . 5: i n t f i s enabled t o be set any t i m e dur i ng t h e q 4 -q 1 cyc l e s . cl kout ( 3 ) ( 4 ) ( 1 ) ( 5 ) ( 1 ) in terru pt l a te ncy ( 2 ) http:///
? 2014 microchip technology inc. ds20005281a-page 93 mcp191 14/5 14. 3 i nter rupt cont rol regi st ers 14. 3.1 i ntcon re giste r th e in tc o n reg i st er is a rea dab le a nd w r it abl e re gis t er , tha t c ont ain s th e v a ri ous en abl e a nd fl ag bit s f or t h e tm r 0 r eg i st er ov er f l ow , i n te r r u pt - o n- c ha n ge an d ex te r n al i n t p i n i nt e r r up t s. note: interrupt flag b i t s are s e t w h en an in terr upt c ond iti on o c c u rs , re gard l es s of th e s t ate of it s c orre sp ond ing en abl e b i t o r the g l ob al en abl e b i t, gi e, i n th e in tc o n reg i s t er . th e us er ? s sof t w a re s h o u ld ens ure the ap pro p ria t e in terru pt fl ag bi t s a r e cl ear pr ior to e nab lin g a n i n terr upt. regis t er 14-1: intcon: inte rrup t control regis t er r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -x g i e pei e t 0i e i n t e i oc e t 0if i n t f i o c f bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7 gi e : gl ob al i n te rrupt enab le bit 1 = e nab les al l u n m a s k e d in terru pt s 0 = d is ab l e s a l l i n t e r r u p t s bi t 6 peie: per i ph eral int e rrup t en abl e b i t 1 = e nab les al l u n m a s k e d pe rip hera l i n ter r upt s 0 = d i s a b le s all pe riph eral in terru pt s bi t 5 t0ie: tmr0 o v e r flow inte rrupt ena b le bi t 1 = e nab les th e tm r0 i n te rrup t 0 = d i s a b le s the tmr0 in terru pt bi t 4 inte: int exte rna l in terru pt en abl e b i t 1 = e nab les th e int ex tern al i n te rrup t 0 = d i s a b le s the in t ex te rnal in terru pt bi t 3 io ce: inte rrup t -on- c h an ge en ab le b i t ( 1 ) 1 = e nab les th e i n terr upt-o n-c h a nge 0 = d is ab l e s t h e i n te r r u pt - o n- c h a n g e bi t 2 t0if : tm r0 o v e r flo w inte rrup t fl ag bit ( 2 ) 1 = t mr 0 reg i s t er h a s ov erfl ow ed (mu s t be cl eare d i n s o f t w a re) 0 = t mr 0 reg i s t er d i d not ov erfl ow bi t 1 intf: ex ter nal int e rrup t fl ag bit 1 = t he ex tern al i n te rrup t oc cu rred (mu s t be cle a re d in s o f t w a re) 0 = t he ex tern al i n te rrup t di d no t o c c u r bi t 0 io cf : i n te r r u pt - o n- c h a n g e i n t e r r u pt f l ag bi t 1 = w he n at le ast one of the in terru pt-on - ch an ge p i n s c han ge d s t ate 0 = n o ne of t he i nte rrup t -on - cha ng e pi ns ha ve ch ang ed st a t e note 1 : i o c x r e gi s t e r s m u s t a l so be en a b l ed. 2: t0 if b i t i s set when tm r0 ro lls o v er . tm r0 i s u n c han ged on res e t a n d sh oul d b e in iti a li ze d b e fo re c l ea rin g t0 if b i t. http:///
MCP19114/5 ds20005281a-page 94 ? 2014 microchip technology inc. 14. 3.1.1 p ie 1 regi st er th e pi e1 re gis t er co nt a i ns th e pe riph eral in terru pt en abl e b i t s , as s how n in r egi st er 1 4-2 . note 1 : bi t pe ie i n the intco n re gis t er m u s t be s e t t o en ab le a n y pe riph era l in terru pt. regis t er 14-2: pi e1 : per iphe ral in t e rrup t e nable regis t er 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? a d i e b clie sspi e cc2i e cc1ie tm r2ie tm r1ie bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7 u n i m pl e m en t e d: rea d as ? 0 ? bi t 6 ad i e : ad c int e rrup t en abl e b i t 1 = e nab les th e ad c i n te rrupt 0 = d i s a b le s the ad c int e rrup t bi t 5 bc l i e : m ssp bus col l i s io n i n terr upt enab le bit 1 = enab les th e m ssp bu s co lli s i on inte rrupt 0 = d i s a b le s the m ssp bus coll is ion int e rrup t bi t 4 sspie: sy nc hron ous se rial port (mss p) inte rrup t ena b l e bi t 1 = e n abl es the mss p int e rrup t 0 = d i s a b le s the m ssp inte rrup t bi t 3 cc 2 i e : ca p t ure 2 /c o m p a re2 int e rrup t enabl e b i t 1 = e nab les th e c a p t ure 2 /c o m p a re2 in terru pt 0 = d i s a b le s the c aptu r e2 /c om p a re 2 i n te rrupt bi t 2 cc 1 i e : ca p t ure 1 /c o m p a re1 int e rrup t enabl e b i t 1 = e nab les th e c a p t ure 1 /c o m p a re1 in terru pt 0 = d i s a b le s the c aptu r e1 /c om p a re 1 i n te rrupt bi t 1 tmr2 ie: t i mer 2 in terru pt en abl e 1 = e nab les th e t i me r2 in terru pt 0 = d i s a b le s the t i m e r2 inte rrup t bi t 0 tmr1 ie: t i mer 1 in terru pt en abl e 1 = e nab les th e t i me r1 in terru pt 0 = d i s a b le s the t i m e r1 inte rrup t http:///
? 2014 microchip technology inc. ds20005281a-page 95 mcp191 14/5 14. 3.1.2 p i e 2 regi st er th e pi e2 re gis t er co nt a i ns th e pe riph eral in terru pt en abl e b i t s , as s how n in r egi st er 1 4-3 . note 1 : bi t pe ie i n the intco n re gis t er m u s t be s e t t o en ab le a n y pe riph era l in terru pt. regis t er 14-3: pi e2 : per iphe ral in t e rrup t e nable regis t er 2 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cdsie ? ? o ti e o vie druvie ovl o ie uvl o ie bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7 c d si e: des a tu rati on de tec tio n in terru pt en ab le bit 1 = e nab les th e d esa t d e t e c t in terru pt 0 = d i s a b le s the desa t detec t i n te rrupt bi t 6- 5 u n i m pl e m en t e d: rea d as ? 0 ? bi t 4 ot i e : o v e r tem p e r atur e interru pt en abl e b i t 1 = e nab les ov ert e m pera t ure in terru pt 0 = d i s a b le s ove r tem p e r atu r e i n te rrupt bi t 3 ov i e : v ou t ov erv o l t age interru pt en abl e b i t 1 = e nab les th e o v in terru pt 0 = d i s a b le s the ov inte rrup t bi t 2 d ruvi e : g a te d r iv e u n d e rv olt age lo ck out inte rrupt ena b le bi t 1 = e nab les g a te d r iv e u v l o inte rrup t 0 = d i s a b le s g a te dri v e uvlo in terru pt bi t 1 ov l oi e : v in o v e r vo lt a ge loc ko ut i nter r upt enab le bit 1 = e nab les o v lo i n terr upt 0 = d is ab l es o v lo i n t er r u pt bi t 0 uv l o i e : v in un derv o l t ag e lo ck ou t int e rrupt enabl e b i t 1 = e nab les uv lo i n te rrupt 0 = d i s a b le s u v lo in terru pt http:///
MCP19114/5 ds20005281a-page 96 ? 2014 microchip technology inc. 14. 3.1.3 p ir 1 re gis t er th e pir 1 r egi ste r co nt a i ns the p e rip hera l in terru pt fl ag bit s , as sh ow n i n r e gist er 14-4 . note 1 : in terru pt fl ag b i t s are se t w hen an in terr upt c o n d it ion oc c u rs , re ga rdle s s of th e s t a t e of i t s c o rres p o ndi ng en abl e b i t or the g l o bal en abl e b i t, g i e, i n the in tc o n regi ste r . the us er ? s s o f t w a re s hou ld e n s u re th e ap pro p ria t e i n terr upt fl ag b i t s are cle a r p r ior t o en abl ing an in terr upt. regis t er 14-4: pi r1: p e r ip her a l inte rrup t f l ag r e gis t er 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? a di f b clif sspif cc2if cc1if tm r2if tm r1if bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7 u n i m pl e m en t e d: rea d as ? 0 ? bi t 6 ad i f : adc in terru pt f l ag bi t 1 = a dc co nve r si on co mp lete 0 = a d c co nve r si on has no t c om ple ted or h as no t be en st a r ted bi t 5 bcl i f : m ssp bu s co lli s i on inte rrupt fla g b i t 1 = i nte rrupt is pe ndi ng 0 = i nte rrupt is no t pe ndi ng bi t 4 sspif: sy nc hro nou s se ria l po rt (m ssp) in terru pt fl ag bit 1 = i nte rrupt is pe ndi ng 0 = i nte rrupt is no t pe ndi ng bi t 3 cc 2 i f : ca ptu r e2/ c o mp are 2 in terru pt f l ag bi t 1 = c a p tu re o r c o m p a r e ha s occ u rr ed 0 = c a p tu re o r co m p a r e has not oc cur r ed bi t 2 cc 1 i f : ca ptu r e1/ c o mp are 1 in terru pt f l ag bi t 1 = c a p tu re o r c o m p a r e ha s occ u rr ed 0 = c a p tu re o r co m p a r e has not oc cur r ed bi t 1 tmr2 if: t i me r2 to pr2 m a t c h interrup t fl ag 1 = t im er2 t o pr 2 ma tch oc cu rred (mu s t be cle a re d i n s o f t w a re) 0 = t im er2 t o pr 2 ma tch di d n o t o c c u r bi t 0 tmr1 if: t i me r1 in terru pt flag 1 = t im er1 r o ll ed ove r (m us t be cl ear ed in s o f t w are) 0 = t im er1 h a s no t rol l ed ov er http:///
? 2014 microchip technology inc. ds20005281a-page 97 mcp191 14/5 14. 3.1.4 p i r 2 re gis t er th e pir 2 r egi ste r co nt a i ns the p e rip hera l in terru pt fl ag bit s , as sh ow n i n r e gis t er 14-3 . note 1 : in terru pt fl ag b i t s are se t w h en an in terr upt c o n d it ion oc cu rs, re ga rdle ss of th e s t a t e of i t s c o rres p o ndi ng en abl e b i t or the g l o bal en abl e b i t, g i e, i n the in tc o n regi ste r . the us er ? s s o f t w a re s hou ld e n s u re th e ap pro p ria t e in terr upt fl ag b i t s are cle a r p r ior t o en abl ing an in terr upt. regis t er 14-5: pi r2: p e r ip he ral inte rrup t f l ag r e gis t er 2 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cdsif ? ? o tif o vif druvif ovl o if uvl o if bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7 cd s i f : desa t det e ct int e rrup t fl ag bit 1 = n or m a l op er a t io n ( c d s p o l = 0 , cdsintp = 0 , cdsintn = 1 ) 0 = d es at u r at i o n d e te c t i o n h a s oc cu r r e d bi t 6- 5 u n i m pl e m en t e d: rea d as ? 0 ? bi t 4 ot i f : o v e r tem p e r atu r e in terru pt fl ag bi t 1 = o v e rte m p e rat u re ev ent has oc cu rred 0 = o v e rte m p e rat u re ev ent has no t oc c u rred bi t 3 ov i f : ov er v o l t ag e in t e rr u p t f l ag bi t 1 =v ou t h a s ex ce ede d th e lev e l d e fi ned by o v _r ef 0 =v ou t i s b e lo w le ve l de fin ed by ov _r ef bi t 2 d ruvi f : g a te d r iv e u n derv o l t ag e lo ck ou t int e rrupt fl ag bit 1 = g at e d r iv e u n de rvol t ag e l oc k ou t h as oc cur r ed 0 = g ate d r ive un d e rv olt age lo ck out has n o t o c c u rre d bi t 1 ov l oi f : v in o v ervo lt a g e loc k out in te rrupt fla g b i t 1 =v in ha s e x c ee ded the le vel de fin ed by ovl o _ d ac 0 =v in i s b elo w le ve l de fin ed by ovl o _d ac bi t 0 uv l o i f : v in un derv o l t ag e l o c k ou t in terru pt f l ag bi t 1 =v in i s b elo w le ve l de fin ed by u v lo _d ac 0 =v in i s abo ve lev e l de fin ed b y u v l o _d ac http:///
MCP19114/5 ds20005281a-page 98 ? 2014 microchip technology inc. 14. 4 c ont ext savi ng dur i ng int e rr upt s du ring a n in terru pt, o n ly the r e turn pc v a l ue i s s a ve d o n th e s t ac k . t y pi cal l y , us er s ma y w i sh to sa ve ke y re gis t er s dur ing a n int e rru pt (e.g ., w and st a t u s re gis t er s). t h is m u s t be im pl em ent ed i n s o f t w are. t e m por ary h o ld in g reg i s t ers w_te mp an d st a t u s _tem p s hou ld b e pl ac ed i n th e la st 1 6 b y te s o f g p r (ref e r to fi gure 1 0 - 3 ). th es e 16 l o ca tio n s a r e c om m o n to al l ba nk s a nd do not requ ire ban ki ng. thi s m ak es c onte x t sa ve an d re sto r e ope rati ons s i m ple r . th e c o d e s how n in e x am pl e 1 4 - 1 c an be us ed t o: ? s tore th e w regi ste r ? s tore th e st a t us reg i s t er ? e x e c u te the isr c ode ? r e s to re th e s t at us (an d ban k sele ct bit) re gi ste r ? r e s to re th e w reg i st er ex amp l e 14-1: s a ving st atus and w r e gis t e r s in ra m t a ble 1 4 -1: s um mar y of re giste r s ass o ciated wi t h inter rupt s na me b i t 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 re g i s t e r on page i n t c on gi e pei e t 0i e i nt e i o c e t 0 i f i nt f i ocf 93 option_reg rapu intedg t0cs t 0 se psa ps2 ps1 ps0 76 pie1 ? adie b cli e sspie cc2ie cc1ie tm r2ie tm r1ie 94 pie2 cdsie ? ? o tie o vie druvie ovl o ie uvl o ie 95 pir1 ? adif b clif sspif ? ? t mr2 i f t mr1 i f 96 pir2 cdsif ? ? o tif o vif druvif ovl o if uvl o if 97 legend: ? = unim p l em en t e d l o c a t i on s , r e ad as ? 0 ?. s had ed c e l l s are no t us ed by inte rrup t s. note: the mcp191 1 4 / 5 d o not r e qu i r e s a v i n g th e pcl a th. ho we ve r , i f co mp u t e d goto s are us ed i n bot h the isr an d the m ai n co de , the pc la th mu st be s av ed a nd r e st ored in the isr . movw f w_tem p ;copy w to temp register swap f statu s,w ;swap status to be saved into w ;swaps are used because they do not affect the status b its movw f statu s_temp ;save status to bank zero status_temp register : :(is r) ;inser t user code here : swap f statu s_temp,w ;swap status_temp register into w ;(sets bank to original state) movw f statu s ;move w into status register swap f w_tem p,f ;swap w_temp swap f w_temp,w ;swap w_temp into w http:///
? 2014 microchip technology inc. ds20005281a-page 99 mcp191 14/5 15 .0 p o w e r- down mode (sl e e p ) th e pow e r-d o w n m o d e i s e n te red by ex ec uti ng a sleep ins t ru cti on. u p on en teri ng sle ep m ode , the fo llo w i ng c o n d it ion s ex is t : 1 . w d t w i l l be cl ear ed but k eep s run n in g, if e nab led for ope rati on duri ng slee p. 2. pd b i t i n t he st a t u s re gis t er is cl eare d . 3. to bit in the st a tus regi ste r is s e t. 4. c p u cl oc k i s d i s a b l ed . 5 . th e ad c i s i nop era b le due to the absen ce of th e 4 v ld o po w e r (a v dd ). 6 . i/ o p o rt s ma int a in t he s t atu s th ey had b e fo re sleep w a s exe c u t ed (d riv i ng h i gh , l o w or h i gh -imped anc e). 7. r e se t s ot h er t h an wd t a r e n ot aff ec t ed by sl eep mo de . 8. a na l og c i r c ui t p o w er ( a v dd ) is re m o v e d d u rin g sl eep mo de . r e fer to in div i d ual ch apt ers for m o re det ail s o n p e rip hera l o per atio n d u rin g sl eep . t o m in im iz e cu r r e nt c o n s um pt i o n , t h e f o l lo w i n g c ond iti ons s hou ld be co nsi d e r ed: ? i / o p i n s s h o u ld no t be flo a ti ng. ? e xt e r na l c i r c ui t r y s i n k i n g cu r r e nt f r om i/ o p i ns . ? i nt e r na l c i r c ui t r y s o u r ci n g cu r r e nt f r om i/ o p i ns . ? c ur rent draw from pi ns wi th int e rna l we ak pu l l- u ps. ? m od ule s u s i ng t i m e r1 o s c i l l at or . i/ o p i ns tha t are hig h -i mp eda nc e in put s s hou ld b e p u ll ed to v dd or gn d ex tern al ly to a v o i d s w itch in g c u rre nt s ca us ed by flo a ti ng i n p u t s . th e sleep in stru cti on re mo ve s pow e r from the an alo g ci r c u i tr y . a v dd i s s h u t do w n t o mi ni mi ze cu r r e n t dr a w in sl eep mo de and to m ai nt a in a s hut d ow n cur r ent of 5 0 a ty pi cal . th e 5v l d o (v dd ) v o l t age dro p s to 2. 5 v ? 3 v i n s l e e p mo de . t h e en a b l e s t a t e of t h e a nal og c i rc ui try d oes not cha n g e w i th t he e x e c ut ion of th e slee p in str u cti o n . 15. 1 w ake- up from sleep th e d evi ce ca n w ak e up f r om slee p th rou gh o ne of th e fo llo w i ng ev en t s : 1. ex tern al r e se t in pu t on mc l r pi n, i f en abl ed 2 . por re se t 3. w a tch dog t i m e r , if e n a b le d 4. an y e x te rnal in terru pt 5. in terru pt s b y pe rip hera l s c a p a bl e of run n in g du rin g sle ep (s ee ind i v i du al p e rip h er al fo r mo re in f o r m a t i o n) th e fi rst tw o ev en t s w i ll ca use a d e v i ce res e t. the las t th ree e v e n t s a r e c ons id ered a co ntin ua tion of pro g ram ex ec uti on . t o de term in e w het her a d evi ce re se t or wak e-up e v e n t oc cur r ed, refe r to se ction 1 3 . 7 ? d eterm i ning the caus e of a res e t ? . th e fo llo w i ng peri phe ral inte rrup t s c a n w a ke the dev i c e fro m slee p: 1. in terru pt-o n-c han ge 2. ex tern al inte rrupt from int pin wh en the sleep i nst ruc t io n is b ein g e x ec ute d, the nex t in s t r u ct i o n ( p c + 1) is p r e f e t c h ed . f o r t h e de v ic e t o w a k e u p thr oug h an int e rrupt ev ent , the co rres pon din g i n terr upt e nab le b i t m u s t be e n ab le d. w a k e -u p w i l l oc c u r rega rdle ss o f the s t ate o f th e gi e b i t. if the g i e bi t i s d i s abl ed, the dev ic e c o n t in ues ex ec uti on at th e in s t r u ct i o n aft e r t h e sleep i n s t ruc t io n. if the g i e bit i s en ab led , th e d e v i ce ex ec ute s the ins t ru cti o n af te r th e sleep i n s t ruc t io n an d w i l l th en c a l l th e in terru pt se rvi c e r o u t in e. in c a s e s w h ere th e ex ec utio n of th e in s t r u ct i o n f o ll o w in g s leep is not des ira b le , the us er s hou ld hav e a n nop af te r th e sleep i n st r u ct io n . t h e w d t i s cl e a r e d w h en t h e de v i c e w a k e s u p f r o m sl eep , reg a rd les s of th e s o u r ce of w a ke -up. http:///
MCP19114/5 ds20005281a-page 100 ? 2014 microchip technology inc. 15. 1.1 w a k e - up usin g interr upt s w hen g l ob al interru pt s a r e dis a b l ed (g ie c l ea red) and a ny in terru pt sou r ce h as bo th i t s in terru pt ena ble b i t a nd i n te rrupt fla g bi t s e t, o n e of th e fo ll ow in g w i l l oc c u r: ? if the in terru pt o c c u rs bef o re th e e x e c ut ion of a sleep ins t ru cti o n - sleep ins t ru cti on w i ll ex ec ute as a n nop - w d t an d wd t pre s c a le r w i l l n o t b e c l ea red -t o bit in the status register will not be set -pd b i t i n t he st a t u s re gis t er w ill no t be cl ea r e d ? if the int e rrup t o c c u rs durin g or a f ter th e ex ec uti o n of a sleep in st r u ct i o n - sleep ins t ruc t i on w i ll be co mpl e te ly ex ec ute d - d ev ic e w i ll im me dia t el y w a ke u p from sle e p - wd t and wd t pres c a le r w i l l be c l ea red -t o b i t i n the status register will be set -pd b i t i n th e st a tus re gis t er w ill be cl eare d ev en i f the fl ag b i t s w e re c hec k e d be fore e x e c u t in g a sleep i n st ruc t io n, it m a y b e po ss ibl e for fl ag b i t s to be co me s et b efo re th e s leep in st ruct ion c o m p le tes . t o de term in e w h eth e r a sle ep in st r u ct ion e x ec ut ed, tes t th e pd bit. if the pd bit is se t, th e sleep in st r u ct i o n w a s e x ec ut ed a s a n nop . figure 15-1: w a k e -up from s l ee p thr o ugh interr upt t a ble 1 5 -1: s um mar y of re giste r s ass o ciated wi t h pow e r-dow n mode nam e bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 regi ster on pa ge i n t c on g i e pei e t 0 i e i nt e i oce t 0 i f i nt f i ocf 93 io ca io ca7 i o c a6 io ca5 ? i oca3 i o ca2 i oca1 i o ca0 12 0 io cb io cb7 i o c b6 io cb5 i ocb4 ? ?i o c b 1 i o c b 0 12 0 pie1 ? a die b clie sspie cc2ie cc1ie tm r2ie tm r1ie 94 pie2 cd s i e ? ? o tie o vie druvie ovl o ie uvl o ie 95 pir1 ? a dif b clif sspif cc2if cc1if tm r2if tm r1if 96 pir2 c d si f ? ? o tif o vif druvif ovl o if uvl o if 97 st a t us irp rp 1 rp 0 t o pd zd c c 69 le gen d : ? = un im ple m e n te d, re ad as ? 0 ?. shaded cells are not used in power-down mode. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc in te rr u p t fl a g gi e b i t ( i ntcon r e g . ) i n st r u ct i o n f l o w pc i n st r u ct i o n fetched instruction executed p c p c + 1 p c + 2 in s t ( p c) = sle e p in s t (p c - 1 ) in s t ( p c + 1 ) sl e e p pr oc ess o r i n sleep in s t (p c + 2 ) in st (p c + 1 ) i ns t ( 000 4h) i ns t ( 000 5h) i n st ( 0004 h) d u m m y c ycl e pc + 2 0 004 h 0005 h du mm y cy cl e t os t pc + 2 no t e 1: gi e = 1 ass u m ed. in t h is ca se a f te r wa ke- up, the pr oce ssor calls t he is r at 000 4h . if gie = 0 , e xe c u t io n will co n t in u e in - lin e . interrupt latency ( 1 ) http:///
? 2014 microchip technology inc. ds20005281a-page 101 mcp191 14/5 1 6 .0 w a tchdog t i m e r (w dt) th e w a t c hd og t i me r is a f r ee ru nni ng ti me r . th e wd t i s e nab led by s e tti ng the wd te b i t i n the c o n f ig re gis t er (def aul t s e tti ng). d u ring nor ma l op era t ion , a wd t ti me -out gen era t es a de v ic e r e se t . if t h e d e v i c e is in s l ee p mo de , a w d t t im e - o ut ca us e s t h e de v ic e t o w a k e up a n d co nt i n ue w i th n o rm al ope rati on. th e wd t ca n be perm a n ent ly dis abl ed by c l e a ri ng th e w d t e b i t i n th e co nfi g re g i ste r . re f e r to se ction 1 1 . 1 ?c o nfigu r a tion w ord? f o r m o re in f o rm at i o n. 16. 1 w at chdog t i mer (wdt) o p e r at ion d u ring nor ma l op era t ion , a wd t ti me -out gen era t es a de v ic e r e se t . if t h e d e v i c e is in s l ee p mo de , a w d t t im e - o ut ca us e s t h e de v ic e t o w a k e up a n d co nt i n ue w i th nor mal ope rati on; th is i s kn ow n as a wd t w a ke-u p. the wd t c a n be pe rma nen tly di sa ble d b y c l e a rin g th e w d t e co nfi gur atio n b i t. th e p os t sc al er a s s i gn me nt i s full y u nd er s of t w a re c ont rol and c an be ch ang ed du ring pro gra m exe c u t io n. 16. 2 w dt per i od t h e w d t ha s a no mi n a l t i m e - o u t pe r i od o f 18 ms ( w it h no pre s c a l e r). t he t i m e -ou t pe rio d s var y w i th te mp erat ure, v dd an d pr o c e s s v a r i a t i o ns f r om par t t o p a rt (refe r to ta b l e 5 - 3 ) . i f l o ng e r t im e - o u t pe r i od s ar e de si red , a p r es ca ler w i th a d i vi si on rati o o f up to 1 : 12 8 c an b e as si gne d to th e wd t un der s o f t w are c o nt rol b y writ ing to th e o p tio n _ r eg regi ste r . thus , tim e -o ut pe rio ds up to 2 . 3 s ec on ds ca n be rea l i z ed . th e clr wdt an d sle ep in str u ct ion s c le a r t h e wd t an d the pre s c a l e r , if as si gne d to the wd t , a nd pre v e n t i t from ti mi ng out and ge nera t in g a de vice re se t. th e t o b i t in t h e s t a t u s r e g i s t er w i l l be c l ea r e d u p on a w a tc hd og t i me r ti me -out. 16. 3 w dt pr ogramm i ng consi d erat io ns und e r wors t-c a s e co ndi tio n s (i .e., v dd =m i n i m u m , t e mp e r at u r e = ma xi mu m, ma xi mu m w d t p r es ca le r ) , i t m a y t a k e se ver a l s e co nd s be for e a wdt time-out occurs. figure 16-1: watchdog timer with shared prescale block diagram t0cki t0se pin tmr0 w a tc hdo g ti m e r wdt ti m e-o u t ps< 2:0 > da t a bu s s e t flag bit t0if on ov erfl ow t0 cs note 1 : t0 se, t0 cs, psa, ps< 2:0 > are bi t s in the o p t i on_reg reg i s t er . 2: wdte bit is in the co nf ig regi st er . 0 1 0 1 0 1 8 8 8-bit prescaler 0 1 f os c /4 psa psa psa wdte sy nc 2 t cy http:///
MCP19114/5 ds20005281a-page 102 ? 2014 microchip technology inc. t a ble 1 6 -1: w d t s t atus condi tions w d t wd te = 0 cleared clrwd t co mm a n d ex it slee p t a ble 1 6 -2: s um mar y of re giste r s ass o ciated wi t h w a tch d og t i me r n a m e b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 regis t er on pag e opt i on_r eg rapu intedg t0cs t0se psa ps<2 : 0> 76 le gen d : sh ade d c ell s are not us ed b y the w atc hdo g t i me r . note 1: re f e r to re g i ste r 1 1 -1 fo r op erat ion of all the bi t s in the c o n f i g regi ste r . t a ble 1 6 -3: s um mar y of configurat ion w o r d w i th w a t c hdog t i m e r nam e bit s bit -/7 b it -/6 b it 13/ 5 b it 12/ 4 b it 1 1 / 3 bit 10 /2 b i t 9/1 b it 8 / 0 re g i s t e r on p a ge config 13 :8 ? ? debug ? wrt1 wrt0 ? boren 79 7:0 ? cp mclre pwrte wdte ? ? ? le gen d : ? = unimplemented location, read as ? 1 ?. shaded cells are not used by watchdog timer. http:///
? 2014 microchip technology inc. ds20005281a-page 103 mcp191 14/5 1 7 .0 flash p r o g ram me mo r y control th e fl as h prog ram me mo ry is rea dab le a nd w r it abl e d u rin g norm a l o pera t io n (ful l v in ra nge ). this m e m o ry is no t di r e c t ly ma pp e d i n t h e r e gi st e r f i l e s p a c e . in ste ad, it is in dire ctl y a ddre s s e d t h rou gh t he s pec ia l fu nc tio n reg i s t ers (ref e r to r e gi s t e r s 1 7- 1 to 17- 5 ). th ere a r e si x sfr s us ed to re ad a nd w r it e thi s me mo r y : ?p m c o n 1 ?p m c o n 2 ?p m d a t l ?p m d a t h ? p madrl ? p madrh w hen int e rfac in g th e pr ogra m m e m o ry bl ock , th e pm d a t l a nd pmd a th reg i s t ers fo rm a tw o - by te w o rd, w h i c h hol ds t he 1 4 -bi t da t a fo r rea d /w rit e , an d th e pmadrl a n d pmadrh re g i ste r s fo rm a two - b y te w or d , w h ic h ho ld s th e 13 - b it a dd r e s s of t h e f l a s h lo c a tio n be in g ac ce ss ed . the s e dev ic es hav e 4k w o rds of pro g ra m fla s h w i t h an ad dres s ran ge fro m 0 000 h to 0ff f h. th e prog ram m e m o ry al low s s i n g le -w ord rea d a nd a b y fo ur-w ord w r ite . a fou r-w ord w r i t e a u tom a t i ca ll y e r as es the row of the loca ti on a n d w r ite s th e ne w da t a (e ras e be fore writ e). th e w r ite tim e is c o n t rol l ed b y an o n -c hi p tim e r . th e w r i t e/e r as e vol t ag es a r e gen erat ed by a n on- chi p ch a r g e pu mp r a t e d t o op e r at e ov er t h e vo l t ag e r a n g e o f the de vi ce for b y t e or word ope rations . w hen the de vi ce is c od e-pro tec t ed , th e c p u ma y co n t i n ue t o r e ad an d w r i t e t h e f l as h p r og r a m me mo r y . d e pen din g o n th e s e tt ing s o f th e fl as h pro g ra m m e m o ry en abl e (wr t < 1 :0 >) b i t s , t he dev ic e ma y or m a y no t be ab le to w r i t e ce rt ai n bl oc ks of the pro g ra m me mo r y ; h o w ev er , r e ad s of th e pr o g r am me mo r y ar e a llo w ed. w hen th e f l as h progr am m e m o ry c o d e pro t ec tio n (cp ) b i t i s en abl ed , the prog ram me mo ry i s c ode -pro tec t ed and the de vi ce p r ogra m m e r (ic s p ) c ann ot acc e s s dat a or prog ram m e m o ry . 17. 1 p madr h and pm adrl regist ers th e pmadrh a n d pm adrl re g i s t e r s c a n a d d r e s s u p t o a ma xi mu m o f 4 k wo r d s of p r og r a m me mo r y . wh en s e le cti ng a prog ram a ddre s s v a l ue, th e m o s t si gni fic ant by te (m sb) of th e add res s is w r itte n to th e pmadrh re g i s t e r a n d th e l e a s t s i g n i f i c a n t byte (l sb) is writ ten to th e pm adrl re gi ste r . 17. 2 p mco n 1 and pm con2 regist ers th e p m c o n 1 r egi ste r i s the co ntro l r egi ste r fo r th e da t a prog ram m em ory ac ces s es. c o n t rol bi ts rd a nd wr in iti a te read an d w r it e, r es p ec ti v el y . i n so ft w ar e , the s e bi ts c an on l y b e s et , no t clea red . they are cl eare d in har d w a re at c o m p le tio n of th e rea d or w r i t e op era t io n. th e in abi lit y t o cl ea r t h e wr bi t i n so f t w a r e p r e v en ts th e ac ci d e n t al pr em ature te rmi nati o n of a w r it e op era t ion . th e wr en bi t, w h e n se t, w i l l al low a w r i t e op era t io n. o n p o w e r- up, the wr en bi t is c l ea r . th e calsel b i t a llo ws the us er to re ad lo ca tio n s i n te st m e m o ry in c a s e the r e are ca lib rati on b i t s sto r ed i n th e c a l i bra t io n w o rd l o c a ti ons th at nee d t o b e tra n s f erre d to sfr t r im re gis t er s. the c a l sel bit i s on ly for r ead s a nd, i f a w r i t e o per atio n i s at tem p te d wi t h cal s el = 1 , n o wri t e wi l l o ccu r . pm c o n 2 i s not a ph ys ic al reg i s t er . r e a d in g p m c o n 2 w i l l re ad a ll ' 0 ' s . t h e p m c o n 2 r e g i st e r i s us ed ex c l us iv el y i n th e flas h m e m o ry w r ite s equ ence. http:///
MCP19114/5 ds20005281a-page 104 ? 2014 microchip technology inc. 17. 3 f l ash progra m m e m o r y cont rol regi ste r s regis t er 17-1: pm da tl: program me mory dat a lo w by te r e gis t er r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 pm da tl <7: 0 > bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7- 5 p m d a tl<7: 0 > : 8 l east signific ant d a t a b i t s to w r ite or r ead from program mem o ry regis t er 17-2: pm adrl: pr o g ram me mory addr es s low by t e re giste r r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 pm adr l <7: 0 > bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7- 0 pm adrl<7 :0 > : 8 l eas t sign ific an t addre s s bit s fo r program m e m o ry r e ad/w r ite op erati o n regis t er 17-3: pm da th: program me mory dat a high by te regis t er u-0 u -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 ? ?p m d a t h < 5 : 0 > bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7- 6 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 5- 0 pmdath<5:0> : 6 most significant data bits from program memory http:///
? 2014 microchip technology inc. ds20005281a-page 105 mcp191 14/5 regis t er 17-4: pm adrh: p r og r a m m e m o r y ad dres s high by te re giste r u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? p madrh<3 : 0 > bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 7- 4 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 3- 0 pm adrh<3 : 0 > : 4 m o s t sig n if ic ant addre s s bi t s or h i gh bit s fo r prog ram m e m o ry r ead s regis t er 17-5: pm con1: p r og ra m me mory control re giste r 1 u-1 r/w-0 u-0 u-0 u-0 r/w-0 r/s-0 r/s-0 ? calsel ? ? ?w r e n w r r d bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n s = bit ca n on ly be se t bi t 7 u n i m pl e m en t e d: re a d a s ' 1 ' bi t 6 c a l sel: pro gram m em ory ca li brat ion sp ac e s ele ct bit 1 = sele c t tes t m e m o ry area fo r rea d s onl y ( f or l oad ing c a li brat ion trim re gis t e r s) 0 = s ele c t use r are a f o r re ads bi t 5- 3 u n i m pl e m en t e d: re a d a s ' 0 ' bi t 2 wren: program m e m o ry w r i t e e nab le b i t 1 = a l l o ws wri t e cy cl e s 0 = i nhi bi t s wri t e to th e eeprom bi t 1 wr: w r ite cont rol bit 1 = i nit i at es a w r i t e cy cl e to pro gra m mem or y . (th e b i t is cl ear ed by hard w are w hen w r it e i s com pl ete . the wr bi t c an onl y b e s e t (not cl eared ) i n s o f t w a r e.) 0 = w ri te c y c l e to the fla s h me mo ry i s com p l e te bi t 0 rd : r ead cont rol bit 1 = i nit i at es a prog ram m e m o ry re ad . (th e read t a ke s one c y c l e . t he r d is c l e a red i n h a rd w a re; the r d bit ca n on ly be se t (no t c l ea red ) in so f t ware .) 0 = d o e s no t in iti a te a fl as h m e m o ry rea d http:///
MCP19114/5 ds20005281a-page 106 ? 2014 microchip technology inc. 1 7 . 3 . 1 r ead i n g th e fl as h p r ogr am me mo ry t o rea d a p r ogra m m e m o ry loc a ti on , the u s e r m u s t w r i t e tw o by tes o f t he ad dres s to th e pmad r l an d pmadrh re g i ste r s, a n d th e n s e t co n t ro l b i t rd (b i t 0 i n th e pm c o n 1 regi st er). o n c e the read co ntro l b i t i s s e t, the prog ram m e m o ry fl ash c ont roll er w i ll us e th e s e c ond ins t ruc t io n c y c l e to re ad th e da t a . th is c a u s e s th e sec o n d ins t ruc t io n im me dia t el y foll ow i ng the bsf pmcon 1,rd in st r u ct i o n t o b e i g no r e d. t h e da ta is a v ai la ble , in the v e ry ne xt c y c l e , in the pm d a tl an d pm d a t h re gis t er s; it c an b e read a s tw o b y te s in th e fo ll ow in g in st ruct ion s . pmd a tl and pmd a th re gis t er s w i l l h o ld thi s v a l ue u n ti l an oth e r re ad o r un til it i s w r i tten to by the us er (d uri ng a w r ite op erat ion ) . ex amp l e 17-1: flash program read figure 17-1: flash program me mory re ad cyc l e e x e cution ? normal m o de banks el pm_adr ; change status bits rp1:0 to select bank with pmadr movlwms_prog_pm_addr ; movwfpmadrh; ms byte of program address to read movlwls_prog_pm_addr ; movwfpmadrl; ls byte of program address to read banks el pmcon1 ; bank to containing pmcon1 bsf pmcon 1, rd ; ee read nop ; fir st instruction after bsf pmcon1,rd executes normal ly nop ; any instructions here are ignored as program ; mem ory is read in second cycle after bsf pmcon1,rd ; banks el pmdatl ; bank to containing pmadrl movfp mdatl, w; w = ls byte of program pmdatl movfp mdath, w; w = ms byte of program pmdatl q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf p m con1 ,rd e x ecu t ed he re inst r ( p c + 1 ) e x ec ute d h e re no p executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 f l a s h addr rd b it i n s t r ( p c) pm dath,pmdatl instr (pc + 3) pc + 3 pc + 4 i n s t r ( p c + 4 ) inst r ( p c + 1 ) i n st r ( p c - 1 ) e xec ute d he re inst r ( p c + 3 ) e xec uted he re inst r ( p c + 4 ) e xe cut ed h er e fl a sh d a t a pm d a th pm da t l re g i ste r e erhlt http:///
? 2014 microchip technology inc. ds20005281a-page 107 mcp191 14/5 1 7 . 3 . 2 w riting to the fl as h p r o g r am me mo ry a w ord o f the fl as h pro gram me mo ry ma y on ly b e wr i tten t o if th e w o rd i s in a n un prot ect ed s egm en t of m e m o ry , as d e fi ned in secti o n 1 1.1 ? c on figur ati o n wo r d ? (bi t s ). flas h program m e mory must be w r itten i n four- w ord blo cks. re fe r t o figu r e s 17-2 and 17-3 for m o re det a ils . a bloc k cons ist s of fou r w ords w i th seq uential add r es s es, w i th a low er bounda r y define d by an add r e s s , w h er e pmad r l <1:0> = 00 . all block w r ites to program m e mory are done as 16-w o rd erase by four-w ord w r i t e operations . the w r ite operation is edg e- a ligned and c annot occ ur across bo undaries. t o w r i t e p r og ram dat a, t he wr en bi t mus t fir s t b e l oad ed i n to the buf fer re gi ste r s (re fer t o fig u re 17- 2 ). th is is a c c om pli sh ed by firs t w r i t in g th e d es t in atio n a d d r e s s to pm adrl a n d pmadrh a n d th e n w r i t i n g th e d a t a to pmda tl a n d pmda th. af ter t he add res s a nd da t a ha ve b e e n se t, the fo ll ow in g se que nc e of e v en t s mu st be exe c u t ed : 1 . w r ite 5 5h, th en aah, to pm c o n 2 (f las h progra m m i n g s e q uen ce) . 2 . se t the wr co ntro l bi t in th e pm c o n 1 regi st er . al l fou r buf fer re gis t er l o c a ti ons sh oul d be wri tten to wi th c o rre ct d a t a . if les s than fou r word s a r e b e in g w r it t e n to i n t h e b l oc k of f o ur w o r d s, a r e a d fr o m t h e p r ogra m me mo ry loc ati on( s) n ot bei ng w r itt en to m us t b e p erfo r me d. t his t a ke s the dat a fr om the pro gra m l o c a tio n (s ) n o t bei ng w r itten and l oad s it into th e pm d a t l and pm d a t h reg i s t ers . the n t he se qu enc e o f ev en t s to t r ansfer da t a t o th e b u f f er re gi ste r s m u s t b e e x ec ut ed. t o trans fer dat a from the bu f f er r e g i sters to the program m e mory , the pmad r l and pmad r h mus t poi nt to the las t location in the four-w ord blo c k ( p m a d r l < 1: 0> = 11 ). then the follow i ng seq uence of ev ent s mu st be exec uted: 1 . w r ite 5 5h, th en aah, to pm c o n 2 (f las h pr o g r am mi ng se qu e n c e ). 2 . se t co ntro l b i t w r in t he pmc o n 1 re gis t er t o b egi n th e w r i t e o pera t io n. th e u s er mu st fo ll ow the sa me sp ec ifi c s equ en ce to i n iti a te t he w r it e for ea ch w o rd in th e pro g ram blo c k , w r i t i n g ea ch p r og r a m w o r d in s e qu en c e ( 000 , 001 , 010 , 01 1 ). whe n th e w r ite is perfo rm ed o n the las t word (pm a drl<1 :0> = 11 ), a b l o c k of si xte en w o rds i s au tom a t i ca ll y era s e d and the c o n t ent o f the f o ur-w o r d bu f f e r re gis t ers a r e w r it ten int o th e p r ogram me mor y . a fte r th e bsf pmco n1,wr i n st r u ct i o n , t h e p r oc es so r re qui res tw o c y c l es to se t u p t he era s e / w r ite op era t io n. th e use r m u s t p l ac e tw o nop i n s t ruc t io ns af ter the wr bi t i s se t. sinc e dat a i s bei ng w r itt en to buf fe r reg i s t ers , th e w r it ing of th e first t h ree w o rds of the b l o c k app ear s to o c c u r im m edi ate l y . th e pro c e s s o r w ill hal t int e rna l op era t io ns for the ty pi ca l 4 m s, onl y du ring th e cy cl e i n w h i c h th e eras e t a k e s p l ac e (i.e ., the la st w o rd of th e s i x t ee n-w o rd bl oc k e r as e). thi s is no t sl eep m o de, a s th e cl oc ks and per iph e ral s w i l l c o nt inu e to ru n. af t e r th e fo ur-w o r d w r i t e c y c l e , th e pr oce s s o r w i ll res u m e op era t io n w i th t he th ird i n s t ruc t io n af t e r the p m c o n 1 w r it e i n s t ruc t io n. t he abo ve se qu enc e m u s t b e re pea ted for t he hig her 12 w o rds . re f e r to fi gur e 1 7 - 2 fo r a b l o c k di ag r a m of t he bu ffe r re gis t ers a nd t he c o n t rol si gn als fo r tes t m o d e . 17. 3.3 p ro te ction again s t s p urious wr i t e th ere a r e c ond iti ons w h e n the dev i c e s hou ld n o t w r i t e to the pro g ra m m e m o ry . t o pro t ec t a g ai ns t s p uri o u s w r it es , v a ri ous m e c h a n is ms h a v e bee n b u i l t in. o n po w e r-u p, w r en is c l ea red. als o , the pow e r-up t i m e r (7 2 m s d u ra tion ) pre v e n t s pro g ra m m e m o ry writ es . th e w r i t e ini t ia te seq u e n ce a nd the wr en b i t hel p pr eve n t an ac cid e n t al w r ite du rin g a po w e r g litc h or s o f t w a re m a l f un cti on. 17. 3.4 o pe rati o n during code pr ot e c t wh en t he d e v i c e is co de- prote c t ed, t he c p u i s ab le to re ad and w r ite un sc ramb l ed d a t a to the pro g ram m em ory . the tes t m ode ac ce ss is d i sa bl ed. 17. 3.5 o pe rati o n during w r ite pr ot e c t wh en t he p r ogra m m e m o ry is w r i t e-p r ote c te d, th e c p u c a n rea d a nd ex ecu t e from th e p r ogr am me mo ry . th e po rtion s of p r ogr am m e m o ry that a r e w r it e-pr otec ted c ann ot be mo di fied b y the c p u us in g th e pmc o n regi st ers. t he w rit e prot ect i on h as n o ef fe ct i n i c s p mo de. note : th e w r ite p r ote c t bi t s are u s e d to prot ect th e u s er ? s prog ram fro m m odi fic a ti on by th e u s er ? s c ode . th ey hav e n o ef fec t w h e n pr o g r am mi ng is pe r f or m e d b y i c s p . t h e c ode -pro tec t bit s , w hen p r og ram m e d for c ode prot ect i on , w ill p r ev ent t he pro g ra m m e m o ry from be ing w r itte n vi a th e ic sp i n ter f ac e. note : an e r ase i s on ly i n it iate d for th e w r i t e of fo ur words, just after a ro w bou nd ary ; or pmco n1 s e t wi th pm adrl<3 :0> = xxxx0011 . http:///
MCP19114/5 ds20005281a-page 108 ? 2014 microchip technology inc. figure 17-2: block w r ite s to 4k flas h pr o g ram me mory figure 17-3: flash program me mory lo ng write c y cle ex e cution 14 14 14 14 program memory buffer register pmadrl<1:0> = 00 buffer register pmadrl<1:0> = 01 buffer register pmadrl<1:0> = 10 buffer register pmadrl<1:0> = 11 pmdatl pm d a t h 75 07 0 6 8 fi rs t word of b l oc k to be writte n if a t ne w row si xte en w o r d s o f fla s h a r e eras ed , then four buffers are transferred to flash automatically after this word is written q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pm co n1 , wr e x ec u t ed he re inst r ( p c + 1 ) e x ecu t ed he re pc + 1 fl a s h ins t r pm d a th , pm d a tl inst r ( p c+3) ins t r nop e xecu t ed he re fl as h fl a sh pm w hlt wr bit p r ocessor halted ee write time pm adrh, p m adrl pc + 3 pc + 4 instr (p c + 3 ) e x ecut ed her e addr da t a me mo r y lo cati o n i gno red re ad pc + 2 inst r ( p c+2 ) ( i nst r ( p c + 2 ) nop e xecu t ed he re (p c ) (p c + 1) http:///
? 2014 microchip technology inc. ds20005281a-page 109 mcp191 14/5 1 8 .0 i/ o po rt s in ge nera l , w h en a pe rip hera l i s e nab led , th at p i n ma y n o t b e u s ed as a gen eral -pu r pos e i / o pin . ea ch po rt ha s the regi st ers for it s op era t ion . t hes e re gis t er s a r e: ? t r i s g p x re gis t ers (d at a dire ct ion reg i st er) ? p o r t g px reg i s t ers (rea d the le vel s o n th e pi ns of th e d e v i ce ) so me port s m ay hav e o ne o r mo re of the foll ow in g a ddi tio nal reg i s t ers . th es e reg i s t ers ar e: ? a n sel x (a nal og se lec t ) ? w pu gpx (wea k p u ll -up ) po rt s w i th an alo g fun c ti on s al so h a v e an an sel x re gist er , w h ic h c a n dis a b l e t he d i gi t a l inp u t a nd s a v e p o w e r . a s i m p l i fi ed mo del of a gen eri c i / o po rt, w i tho u t th e i n te rfac es to oth e r p e ri phe rals , i s sh ow n i n fi gu re 18 -1 . figure 18-1: gene ric i / o portgpx ope ration ex amp l e 18-1: initializi ng po rtg p a 18. 1 p ortgp a an d tri s g p a regi ste r s po r t g p a i s an 8 - bi t w i de, b i di rec t io nal p o rt c o ns is tin g of fi ve c m o s i / os , one o p en-d r ai n i/ o and on e op en-dr ai n in put-o nl y pi n (g p a 4 i s no t av ail a bl e). th e c o rre spo ndi ng dat a di rec t io n reg i s t er i s tr is gp a. se ttin g a trisg p a b i t t o 1 w ill m ak e t he co rres pon din g po r tg p a pi n a n in put (i.e ., d i s abl e th e o u tpu t dri v e r). c l e a ri ng a t r i s gp a bi t set t o 0 w ill m a k e th e c o rre spo ndi ng po r t g p a pin an ou tput (i.e ., e n ab le s ou tpu t dri v e r). the ex ce pti on i s g p a5 , w h i c h is i n p u t on ly a nd it s t r isg p a bit w i l l alw a ys re ad as ? 1 ?. ex am ple 1 8 - 1 s h o w s h o w to init ia lize an i / o port . r e a d i ng th e po r t gp a reg i s t er read s th e s t at us of th e pi ns , w he r ea s w r i t in g to it w i ll w r ite to the por t la tc h. al l w r it e o pera t io ns are read -mo d if y-w r i t e o pera t io ns . th e tr isgp a reg i s ter co ntro ls th e po r t g p a pi n ou tpu t driv ers, ev en w h e n the y are b e in g us ed a s an al og in pu t s . t he us er m u s t ens ure the b i t s in th e tr is gp a re gi ste r a r e ma int ain ed se t w h en us in g them as an al og i npu t s . i/o pi ns co nfi g ure d a s a n al og i n p u t al w a y s re ad ? 0 ?. if th e pi n i s c o nf igu r ed for a dig i t a l o u t p ut (e i t he r p o r t or al t e r n a t e fu n c t i on ) , t h e tr is g p a bi t mu st b e cl eare d in o r de r f o r the pin t o driv e th e s i gn al and a r ead will ref l ec t th e s t at e of the pi n. 18. 1.1 i nte rrup t-on-cha nge ea ch po r t g p a pi n i s ind i v i du all y co nfigura b le as a n i n terr upt-o n-c h a nge pin . c o n t rol bi t s ioc b < 7 :4 > an d io cb<2 :0> e nab le or di sa ble the inte rrup t fun c ti on f o r ea ch pin . th e in terru pt-o n-chan ge fe atu r e is di sa ble d on a pow e r-on r e se t. r e fe renc e se ction 1 9 . 0 ? i nte r rup t-o n-chan ge? for mo re in fo rma t ion . 18. 1.2 w e a k pu ll- up s por t g p a <3:0 > and p o r t gp a 5 have an inter nal w eak pull- up. por t gp a< 7:6> do not have i nter nal w eak pull- up s. individu al contr o l bits can enab le or d i sable t h e inte rnal w eak pull- up s (r e f e r t o r egi s t er 18-3 ). t he w eak pull- up is automat ically tur ned of f w hen the por t pin is confi gured as an ou tput, an alt ernat ive f unction or on a pow e r - on r e set set t ing the r a pu bit in t h e opti o n _r eg reg i ster . the w e ak pull- up on gp a 5 is enabl ed w hen con f igured as mclr pin by sett ing b i t 5 in the c o n f ig regi s t er , and disabl ed w h e n g p a 5 is an i / o. there is no software control of the mclr pull-up. q d ck write latx data register read p o r t gp x wr i t e p o r t g p x t r is gp x read latx data bus t o pe ri ph er a l s anselx v dd v ss i/o pin ; this code example illustrates ; initializing the portgpa regi ster. the ; other ports are initialized i n the same ; manner. banksel portgpa; clrf portgpa;init porta banksel ansela; clrf ansela;digital i/o banksel trisgpa; movlw b'00011111';set gpa<3:0> as ;inputs movwf trisgpa;and set gpa<7:5> as ;outputs http:///
MCP19114/5 ds20005281a-page 110 ? 2014 microchip technology inc. 1 8 . 1 . 3 a n s el a r e gi ste r th e an sela regi ste r i s us ed to co nfi gur e t he inp u t m o d e of a n i/ o p i n t o an alo g . se ttin g th e ap prop ria t e an sel a bi t h i gh w i ll ca use a ll dig i t a l read s on the pi n t o b e r e ad as ? 0 ? a nd all o w a nal og func ti ons on th e pi n to op erat e c o rre ctl y . th e s t at e o f the an sela bit s h a s no ef f e c t on dig i t a l ou t p ut f u nc ti o n s . a pi n w i t h t r i s gp a c l e a r ed a n d anselx s e t will st ill ope rate as a dig i t a l ou tpu t, b u t th e in put m ode w i ll be an al og. th is ca n ca us e u nex pe cte d b eha vi or w he n ex ec uti ng read -mo dif y-w r i t e i n s t ruct io ns on the af f e c t ed port. 18. 1.4 p or tg p a f u nctions and output p r ioritie s ea ch po r t g p a pi n is m u lti p le xed w i th othe r fu nc tion s. th e p i ns , th eir co mbi ned fun c ti ons an d th eir outp u t p r iorit i es are s how n i n t able 18-1 . for a ddi tion al i n form ati on, re fer to the a pprop riate se cti on in thi s da t a s hee t. pin g p a7 i n th e por t gp a re gis t er is a true ope n-dra i n p i n w i t h no con nec tio n ba ck to v dd . w hen m ul t ip le o utpu t s a r e en abl ed, t he ac tu al pi n c ont rol goe s t o th e p e rip heral wi th t he h i g hes t p r iori ty . an alo g in put func ti ons, su ch as a d c , a r e n o t s how n i n th e prio rity lis t s . t hese in put s are ac ti ve w h e n the i/o pi n i s se t f o r a n al og mo de u s i n g t h e a n s e l a r e g i s t er . d i git a l outp u t fun c ti ons m a y c o n t rol th e p i n w hen i t is i n an alo g m o d e wi t h th e p r iori ty sh ow n i n ta b l e 1 8 - 1 . note : th e an sela bi t s de fau l t to th e anal og m o d e af t e r r e s e t. t o u s e any pi ns as d i gi t a l gen eral -pu r pos e o r p e ri phe ral i npu t s , th e co rres pon di ng an sel bi t s mu st be in it i a li ze d t o ? 0 ? by t he us er ? s so ftw ar e . t able 1 8 -1: p ortgp a output p r iority pin na me function priority ( 1 ) gp a0 g p a 0 te st_o u t gp a1 gp a1 clkpi n gp a2 gp a2 t0 cki int gp a3 gp a3 g p a5 g p a5 (op en- drai n, i n pu t o n ly ) mcl r test _en gp a6 gp a6 ccd icspda t g p a7 g p a7 (op en- drai n o u tpu t, st in pu t) scl note 1 : o u tp ut f unc tio n p r ior i ty li ste d from lowest to highest. http:///
? 2014 microchip technology inc. ds20005281a-page 111 mcp191 14/5 regis t er 18-1: portgp a : p o rtgp a re giste r r/w - x r /w -x r-x u -0 r/w - x r /w -x r/w - x r /w -x gpa7 gpa6 gpa5 ? g pa 3 g pa 2 g pa 1 g pa 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 gp a 7 : gen e ra l-purp os e ope n -drai n i / o pin 1 = p ort p i n is > v ih 0 = p ort p i n is < v il bi t 6 gp a 6 : g e n e ra l-purp os e i/ o pin 1 = p ort p i n is > v ih 0 = p o r t pi n i s < v il bi t 5 g p a5 /mclr/test _ e n5 : ge ner al-pu r pos e op en-d r a i n inp u t p i n bi t 4 u n i m pl e m en t e d: rea d as ? 0 ? bi t 3- 0 gp a < 3: 0 > : gen e ra l-purp os e i/ o p i n 1 = p ort p i n is > v ih 0 = port pin is < v il reg i s t er 18- 2: t r is gp a: po rtgp a t r i-s t ate r e gis t e r r/w - 1 r / w -1 r-1 u -0 r/w - 1 r /w -1 r/w - 1 r /w -1 trisa7 trisa6 trisa5 ? t risa3 trisa2 trisa1 trisa0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 tr isa <7: 6> : po r t gp a t r i - s t ate c ontro l b i t 1 = p or tg p a p i n co nfig ure d as a n in pu t (tri -st a ted ) 0 = p or tg p a p i n co nfig ure d as a n ou tpu t bi t 5 trisa5: gp a5 po rt t r i - s t a t e c o ntro l b i t this b i t i s a l way s ? 1 ? as g p a5 is an inp u t o n l y bi t 4 u n i m pl e m en t e d: rea d as ? 0 ? bi t 3- 0 tr isa <3: 0>: po r t gp a t r i - s t ate c ontro l b i t 1 = p or tg p a p i n co nfig ure d as a n in pu t (tri -st a ted ) 0 = p or tg p a p i n co nfig ure d as a n ou tpu t http:///
MCP19114/5 ds20005281a-page 112 ? 2014 microchip technology inc. regis t er 18-3: w p ugp a : w e ak p u ll-up portgp a r e gis t e r u-0 u -0 r/w - 1 u -0 r/w - 1 r /w -1 r/w - 1 r /w -1 ? ? wpua5 ? w pua3 wpua2 w pua1 wpua0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 u n i m pl e m en t e d: rea d as ? 0 ? bi t 5 wpua5 : w e a k pu ll -up r e gi ste r bi t 1 = p ull - up ena ble d 0 = p ul l - up di sa b l e d bi t 4 u n i m pl e m en t e d: rea d as ? 0 ? bi t 3- 0 wpua<3 :0 > : w e a k pu ll- up r e gis t e r bit 1 = p ull - up ena ble d 0 = p ull - up dis ab l ed note 1 : th e w e ak pul l-u p de vi ce is en abl ed onl y w h en the glo bal rapu bi t is en a b l e d, t h e pi n i s i n i n pu t mo de (t r i sg p a = 1 ) an d th e i ndi vi dua l w p u a bit is en abl ed (wpu a = 1 ), an d th e p i n is not co nfi gure d a s a n a nal og inp u t. 2: g p a5 w ea k p ul l -up is al so en abl ed w h en the pin is c onf igu r ed as mc l r in the c o n f i g regi ste r . regis t er 18-4: ans ela: ana l og s e le ct gp a r e gis t e r u-0 u -0 u-0 u -0 r/w -1 r /w -1 r/w -1 r /w -1 ? ? ? ? ansa3 ansa2 a n sa 1 a nsa0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 3- 0 a n s a <3 : 0 >: ana l og sel e c t gp a re gis t e r bi t 1 = a nal og inp u t. pin i s assi g ned as an al og i n p u t. ( 1 ) 0 = d i g i t al i/o . pi n is a s s i gn ed to p o rt o r s pec ia l fu nc tion . note 1 : se ttin g a pin to an ana log in put aut om ati c al ly di sa ble s t he d i g i t a l in put ci rcu i try , w eak pu ll -up s and i n ter r upt- on-c h a nge if av ail abl e. t he cor r esp o n d in g tr i s a bi t m u st be se t to inp u t m o d e i n o r der to a llo w e x te rnal c ontro l o f th e v o lt age on the pi n. http:///
? 2014 microchip technology inc. ds20005281a-page 113 mcp191 14/5 t able 1 8 -2: s um mar y of re gist e r s ass o ciated wi t h portgp a name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b i t 0 re g i s t e r on page ansel a ? ? ? ? ansa3 ansa2 ansa1 ansa0 11 2 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 76 portgpa gpa7 gpa6 gpa5 ? gp a3 gp a2 g p a1 g p a0 111 trisgpa trisa7 trisa6 trisa5 ? t r isa3 trisa2 trisa1 trisa0 111 wpugpa ? ? wpua5 ? w pua3 wpua2 w pua1 wpua0 11 2 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portgpa. http:///
MCP19114/5 ds20005281a-page 114 ? 2014 microchip technology inc. 18. 2 p ortgpb and trisgpb regi ste r s d u e to s p ec ia l f u n c ti o n pi n r e qu i r em en ts, a l i m i t ed n u m ber o f th e po r tg pb i/ os are uti l i z ed . o n th e 2 4 -pi n qf n m c p 191 14 , gpb0 a nd gpb 1 a r e i m p l em en ted . gpb 0 is an ope n-dra i n g e n e ral - pur pos e i/ o an d sd a p i n. g pb1 is a gen eral-pu r pos e i/o , a nal og in put an d vr ef2 d a c ou tpu t. t he 28-p i n q f n m c p19 1 1 4 h a s fou r ad diti on al g e n e ral - pur pos e po r t gpb i/o pi ns. t he c o rres p o ndi ng d a t a d i rec t io n re gis ter i s t r i s gpb. setti ng a tr isgpb bi t to 1 wi l l m a k e th e c o rres p o ndi ng po r t gpb p i n an i npu t (i.e ., d i s abl e the o u tp ut dri v e r). c l e a rin g a tr isgpb bi t to 0 w i ll ma ke th e co rres pon din g po r t g pb p i n an o u tp ut (i .e., ena ble the out put d r iv er). ex am pl e 1 8-1 sh ows h ow to ini t ia li ze an i / o por t. so m e pi ns fo r por t g pb are m u l t ip lex e d wit h a n a l ter nate fun c ti on for th e pe rip heral or a cl oc k fu nc tio n . in ge neral , w h e n a peri phe ral or c l oc k func tio n i s e nab led , t hat pi n ma y not be u s e d a s a g ene ral- purp o s e i/o p i n. r e adi ng th e po r t g pb regi st er rea d s th e st atu s of th e p i ns , wh erea s wri t in g to it will write to the po r t l a tc h. al l w r i t e o perat io ns are read -mo d i f y-w r i t e o p e r ations . th e trisg pb re gis ter co ntro ls the po r t g p b pin o u t- p ut dri v e r s, ev en w h en th ey ar e bei ng us ed a s an alo g i npu t s . t he us er sh oul d en sure t he bi t s i n the tr isg p b re gis t er are m a i n t a i n e d s e t w hen u s i ng the m as an alo g i npu t s . i/o pin s co nfi gure d a s an alo g i npu t a l w a y s rea d ? 0 ?. if th e pi n is c o n f ig ured f o r a di git a l ou tpu t (eit her p o rt o r a l te rnat e func ti on), th e tr isg pb b i t m u s t b e cl eare d i n o r de r fo r th e p i n to dri v e th e s i g nal a nd a read w i l l re fle c t t he st a t e o f th e p i n. 18. 2.1 i nte rrupt - on-cha nge ea ch por t g pb pi n i s i ndi vi dua lly c onf igu r abl e a s a n i n ter r upt -on-c h a nge pi n. c o ntrol bi t s io c b <7:4 > an d i o c b < 2 : 0 > en ab l e o r d i s a b l e t h e i n te r r u pt f u nc t i o n f o r e a ch pi n. th e in terru pt-o n-chan ge f eatu r e i s di sa ble d o n a pow e r-on r e se t. r e fe renc e se ction 1 9 . 0 ? i nte r ru pt-o n-chan ge? fo r mo re i n fo rma t io n. 18. 2.2 w e a k pu ll- up s ea ch of t he por t g pb pi ns ha s a n i n di vi dua ll y c onf igu r abl e i n te rnal w e a k p u ll -up. c ont rol bit s wpu b < 7 :4 > a nd wpu b <1 > en ab le or d i s abl e e a c h pu ll -up (refe r to r e gi st e r 18 - 7 ). ea ch w e a k pul l-up i s au tom at i ca ll y tu rned of f w h en t he p ort pi n is co nfi gure d as a n o u tp ut. a ll pul l-up s are dis a b l ed on a pow e r-o n res e t by the rapu bi t in the o p tio n _r eg re gis t er . 1 8 . 2 . 3 a n s el b r e gi ste r th e an selb regi ste r i s us ed to co nfi gure th e inp u t m ode of a n i/o p i n to an alo g . se ttin g th e ap prop ria t e an sel b bi t h i gh w i l l ca use a ll dig i t a l r ead s on the pi n to be rea d as ? 0 ? a nd all ow an al og func tio n s on the pi n to op erat e c o rrec t l y . the s t ate of the a n selb bit s has n o ef fect on the digit a l output func t i ons. a pin w i th tr isgpb clear and an s e lb set w ill still op er a t e as a d i git a l output, but the input mode w i ll be analog. this can cause unexp e cted beha vior w hen ex ecuting read-modi f y -w rite instruc t i ons on the af fected port. the tr i s gpb r egister cont rols the p o r t gpb pin outpu t dri v ers, even w hen they are being used as analog inputs. the user shoul d ensu r e the bit s in t he t r i s gpb r egister are maintained set w hen using them as a nalog inputs. i/o pins c o nfigu r ed as anal og inp u t a l w a ys read ? 0 ?. note : th e an selb bi t s de fau l t to th e anal og m ode af t e r r e s e t. t o u s e any pi ns as di gi t a l g e n e ral - pur pos e or p e ri phe r al in pu t s , the co rres pon din g an sel b bi t s m u s t be in iti a li ze d to ? 0 ? by t h e u s er ? s so ft war e . http:///
? 2014 microchip technology inc. ds20005281a-page 115 mcp191 14/5 18. 2.4 p or tg p b functions and output p r ioritie s eac h por t gpb pi n i s mu ltip lex ed w i th oth e r fu nc tion s. th e p i ns , th eir com b i ned fun c ti ons an d th eir outp u t p r iorit i es are s how n i n t able 18-3 . for a ddi tion al i n form atio n, re fer to the a pprop riate se cti on in thi s da t a s hee t. g pb0 pi n in the por t gpb reg i st er is a tru e ope n-dra i n p i n w i t h no con nec tio n ba ck to v dd . when m ul t ip le o utpu t s a r e en abl ed, t he ac tu al pi n c ont rol goe s t o th e p e rip hera l w i th t he h i g hes t p r iori ty . an alo g i n p u t f unc tio n s , s u c h a s ad c , an d som e dig i t a l i npu t fun c ti ons are n o t i n cl ud ed in the l i s t bel ow . t hese i npu t s a r e a c ti ve w hen the i/o pin is se t for an alo g mo de us i n g th e a n s e l b r e g i st er . d i gi tal ou t p u t fu nc tio n s m a y c ontr o l th e pi n w h en i t is in an al og m ode, wi th th e p r ior i ty sh own in t a b l e 18-3 . t able 1 8 -3: p ortgp b output p r iority pin na me f uncti on prio r i ty ( 1 ) gp b 0 gp b 0 (o p e n - d r ai n i n pu t / o u t pu t ) sda gpb1 gpb1 vref2 gpb4 gpb4 ( m c p 1 91 14 ) icspda t gpb5 gpb5 ( m c p 1 91 14 ) gpb6 gpb6 ( m c p 1 91 14 ) gpb7 gpb7 ( m c p 1 91 14 ) ccd2 note 1 : o u tp ut f unc tio n p r ior i ty li ste d fro m lowe st to hi ghe st. reg i s t er 18- 5: po rt g p b: portgpb regis t er r/w - x r /w -x r/w - x r /w -x u-0 u -0 r/w - x r /w -x gpb7 ( 1 ) g pb6 ( 1 ) gpb5 ( 1 ) gpb4 ( 1 ) ? ? g pb1 g pb 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ?0 ? u = b i t i s u n c han ged x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 gp b < 7 : 4> : ge ne ral-pu rpo s e i/o pin bi t 1 = p ort p i n is > v ih 0 = p ort p i n is < v il bi t 3- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1- 0 gp b < 2 : 0> : ge ne ral-pu rpo s e i/o pin bi t 1 = p ort p i n is > v ih 0 = p ort p i n is < v il note 1 : mc p 1 9 1 15 on l y . http:///
MCP19114/5 ds20005281a-page 116 ? 2014 microchip technology inc. regis t er 18-6: tris g p b: p o rtgp b t r i - s t ate regis t er r/w -1 r / w -1 r/w -1 r / w -1 u-0 u -0 r/w -1 r /w -1 trisb 7 ( 1 ) trisb6 ( 1 ) t r isb5 ( 1 ) trisb4 ( 1 ) ? ? trisb1 trisb0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 tr isb <7: 4> : g e nera l -pu r pose i / o pin bit 1 = p ort p i n is > v ih 0 = p ort p i n is < v il bi t 3- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1- 0 tr isb <2: 0> : g e nera l -pu r pose i / o pin bit 1 = p ort p i n is > v ih 0 = p ort p i n is < v il note 1 : mc p 1 91 15 on l y . regis t er 18-7: w p ugpb: w e ak pull-up portgpb regis t er r/w - 1 r / w -1 r/w - 1 r / w -1 u-0 u -0 r/w - 1 u -0 wpub7 ( 2 ) wpub6 ( 2 ) wp u b 5 ( 2 ) wpub4 ( 2 ) ? ? wpub1 ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 wpu b <7:4 > : w e a k pu ll -up r e gi ste r bi t 1 = p ull - up ena ble d 0 = p ull - up dis ab l ed bi t 3- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1 wpu b <1> : w eak pul l -u p r e g i s t er b i t 1 = p ull - up ena ble d 0 = p ull - up dis ab l ed bi t 0 u n i m pl e m en t e d: re a d a s ? 0 ? note 1 : th e w e ak pul l-u p de vi ce is en abl ed onl y w h en the glo bal r apu bi t is en a b l e d, t h e pi n i s i n i n pu t mo de (t r i sg p a = 1 ) an d th e i ndi vi dua l w p u b bit is en abl ed (wpu b = 1 ), an d th e p i n is not co nfi gure d a s a n a nal og inp u t. 2: mc p 1 91 15 on l y . http:///
? 2014 microchip technology inc. ds20005281a-page 117 mcp191 14/5 regis t er 18-8: ans elb: ana l og s e le ct gpb regis t er u-0 u-0 r/w-1 r/w-1 u-0 r/w-1 r/w-1 u-0 ? ? ansb5 ( 1 ) ansb4 ( 1 ) ? ansb2 ansb1 ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 5- 4 an s b < 5 : 4 > : ana l og sel e c t gp a regi s t e r bi t 1 = a nal og inp u t. pin i s ass i g ned as an al og i n p u t ( 1 ) . 0 = d i g i t al i/o . pi n is a s s i gn ed to p o rt o r s pec ia l fu nc tion . bi t 3 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 2- 1 an s b < 2 : 1 > : ana l og sel e c t gp a regi s t e r bi t 1 = a nal og inp u t. pin i s ass i g ned as an al og i n p u t ( 1 ) . 0 = d i g i t al i/o . pi n is a s s i gn ed to p o rt o r s pec ia l fu nc tion . bi t 0 u n i m pl e m en t e d: re a d a s ? 0 ? note 1 : mc p 1 9 1 15 on l y . 2: se ttin g a pin to an ana log in put aut om ati c al ly di sa ble s t he d i g i t a l in put ci rcu i try , w eak pu ll -up s a n d i n ter r upt- on-c h a nge if ava i l abl e. t he c o rr esp ond in g tr is bit mu st be set to i n pu t m o de in ord e r to al low e x te rnal c ontro l o f th e v o lt age on the pi n. t able 1 8 -4: s um mar y of re gist e r s ass o ciated wi t h portgpb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 re g i s t e r on page ansel b ? ansb6 ( 1 ) ansb5 ( 1 ) ansb4 ( 1 ) ? ? ansb1 ? 11 7 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 76 portgpb gpb7 ( 1 ) gpb6 ( 1 ) gpb5 ( 1 ) gpb4 ( 1 ) ? ? gpb1 gpb0 11 5 trisgpb trisb7 ( 1 ) trisb6 ( 1 ) trisb5 ( 1 ) trisb4 ( 1 ) ? ? t r i sb1 t r i sb0 11 6 wpugpb wpub7 ( 1 ) wpub6 ( 1 ) wpub5 ( 1 ) wpub4 ( 1 ) ? ? wpub1 ? 11 6 le gen d : ? = uni mp lem en t ed loc at i on s, read as ? 0 ? . sh ade d c ell s are n ot use d b y t he p o r t gp b reg i st er . note 1: mcp 1 9 1 15 on l y . http:///
MCP19114/5 ds20005281a-page 118 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 119 mcp191 14/5 1 9 .0 inte r rupt- on- c h ange ea ch po r t g p a and po r t gpb pi n is i ndi vi dua ll y c onf igu r ab le as a n int e rrup t -on - ch ang e pin . c o ntro l bit s io c a and i o c b en abl e or dis a b l e th e inte rrup t f unc tio n fo r ea ch p i n . refe r to r e gi st e r s 1 9- 1 and 19-2 . the interrupt-on-cha nge is dis abled on a pow e r-on r e set. the interrupt-on-cha nge on gp a5 is di sabled w hen c onfigured as m c lr pin in the c o n f ig r e gister . for ena bled interrupt-on-cha nge pins , the valu es are c omp ared w i th t h e old v alue la tched on the las t read of portgp a o r por t g p b. the mis m atch ed output s of the last read of all the por t g p a an d por t g p b pins are or ?ed together to set t h e interrupt-on-c hange interrupt flag (ioc f) bit in the in tc o n reg i ster . 19. 1 e nabl in g t h e modul e t o allow in dividua l port pin s to generate an interrupt, the io c e bit in the in tc o n reg i ster must be s e t. i f the io c e bit is dis abled, the edge detec tion on t h e pin w ill still oc cur , but an interrupt w ill not be gene r a te d. 19. 2 i ndiv i dual pi n conf i gurat ion t o enab le a pin to detec t an interrupt-on-change , the as socia t e d io ca x o r io c b x bit in the io ca or io c b regis t ers is set. 19. 3 c l eari ng i n t e rrup t flags the user , i n the in t e r r upt s e r v ice r outin e, clea r s the interrupt by : a ) an y read o f p o r t g p a or po r t gpb and c l ear fl ag bi t io c f . th is w i ll en d the mi sm atc h c ond iti on. or b ) an y writ e of por t g p a or por t g pb and c l ear fl ag bit i o c f w i ll end the mi sm atc h c ond iti on. a m i s m a t ch co ndi tio n wil l c onti n u e to s e t f l ag bit io cf . r e adi ng po r tg p a or por tg pb w ill e nd th e m i s m a t ch co ndi tio n an d a llo w flag bi t io c f to b e cl ea r e d. t h e l a tc h ho ld i n g t h e l a s t r e a d va lu e is no t aff e c t ed by a m c l r res e t. af te r th is res e t, the io cf fl ag w ill co nti nue to be set if a m i s m a t ch is pre s e nt. 19. 4 o per a ti on i n sl eep the interr u pt- on - c hange in t e r r upt s equenc e w i ll w ake the de vice from slee p mode, if the io c e bit is s e t. note : if a ch ang e on the i / o p in s h o u ld oc cur whe n any por t g p a or por t g p b o pera t io n is be in g ex ec ute d , the i o c f i n ter r upt fla g m a y no t ge t se t. http:///
MCP19114/5 ds20005281a-page 120 ? 2014 microchip technology inc. 19. 5 i nter rupt -on- change reg i st ers regis t er 19-1: ioca: inte rrup t- on-change p o rtgp a re g i s t er r/w - 0 r / w -0 r/w - 0 u -0 r/w - 0 r /w -0 r/w - 0 r /w -0 io c a 7 i o c a6 i o c a 5 ? io ca3 i o c a 2 io c a 1 i o c a 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 i o ca< 7 : 6 > : inte rrup t -on - c han ge p o r t gp a re gis t e r bit s 1 = i nte rrupt -on-c h a nge en abl ed on the pin . 0 = i nte rrupt -on-c h a nge di sa ble d o n th e p i n. bi t 5 i o ca< 5 > : in terru pt-o n-cha n g e po r t g p a reg i s t er b i t s ( 1 ) 1 = i nte rrupt -on-c h a nge en abl ed on the pin . 0 = i n t erru pt-o n-ch an ge d i s abl ed on the pin . bi t 4 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 3- 0 i o ca< 3 : 0 > : inte rrup t -on - c han ge p o r t gp a re gis t e r bit s 1 = i nte rrupt -on-c h a nge en abl ed on the pin . 0 = i nte rrupt -on-c h a nge di sa ble d o n th e p i n. note 1: the interrupt-on-change on gpa5 is disabled if gpa5 is configured as mclr . regis t er 19-2: iocb: inte rrup t- on-change p o rtgp b re g i ste r r/w -0 r / w -0 r/w -0 r / w -0 u-0 u -0 r/w -0 r /w -0 iocb7 ( 1 ) io c b 6 ( 1 ) io c b 5 ( 1 ) io cb 4 ( 1 ) ? ?i o c b 1 i o c b 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 i o cb< 7 : 4 > : inte rrup t -on - c han ge p o r t gp b reg i st er b i t s 1 = i nte rrupt -on-c h a nge en abl ed on the pin . 0 = i nte rrupt -on-c h a nge di sa ble d o n th e p i n. bi t 3- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1- 0 i o cb< 1 : 0 > : inte rrup t -on - c han ge p o r t gp b reg i st er b i t s 1 = i nte rrupt -on-c h a nge en abl ed on the pin . 0 = i nte rrupt -on-c h a nge di sa ble d o n th e p i n. note 1 : mcp19115 only. http:///
? 2014 microchip technology inc. ds20005281a-page 121 mcp191 14/5 t able 1 9 -1: s um mar y of re giste r s as s o ciated wi t h inter rupt-on-change name bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 re gi s te r on pa ge ansel a ? ? ? ? a nsa3 ansa2 ansa1 ansa0 11 2 ansel b ? a nsb6 ( 1 ) ansb5 ( 1 ) ansb4 ( 1 ) ? ? a nsb1 ? 11 7 intcon gie peie t0ie in te ioce t0i f intf io cf 93 io ca ioca7 ioca6 ioca5 ? i oca3 i o ca2 i oca1 i o ca0 120 io cb io cb7 ( 1 ) io cb6 ( 1 ) io c b 5 ( 1 ) io cb4 ( 1 ) ? ?i o c b 1 i o c b 0 120 tri s g p a trisa7 trisa6 trisa5 ? t risa3 trisa2 trisa1 trisa0 111 tri s g p b t risb7 ( 1 ) t r isb6 ( 1 ) tri sb5 ( 1 ) trisb4 ( 1 ) ? ? t risb1 trisb0 11 6 le gen d : ? = u n im pl em ent ed l o c a ti ons , re ad as ? 0 ?. sha ded ce lls a r e no t u s ed by in terru pt-o n-c han ge. note 1 : mcp19115 only. http:///
MCP19114/5 ds20005281a-page 122 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 123 mcp191 14/5 20 .0 inter nal t e mp e rature indicator module th e m c p19 1 14/ 5 ar e eq ui ppe d w i th a tem p e r atu r e c i rc uit des ig ned to m eas ure t he o pera t in g tem p e r atu r e o f t he s ili co n di e. the c i rc ui t' s ran ge of o per atin g te mp erat ure fa lls betw e en -40 c a nd +1 25c . th e o utpu t is a vo lt a ge t hat i s pro po r tion al t o the dev ic e temperat ure. th e o u tpu t o f th e t e m pera t ure in dic a to r i s i n ter nal ly co nne cte d t o th e de vi ce ad c . 20. 1 c i r cui t operat ion th is i n te rnal t e m pera t ure m e a s u r em ent c i rc uit i s a l w ay s ena ble d. figure 20-1: t e mp e rature circui t diagram 20. 2 t emperat ure output the output of the circuit is measur ed using the inter nal analog- to-d igit al converter . c hanne l 13 is reser v ed fo r the temperat ure cir c uit out put. r e fer to sect ion 2 1.0 ?ana log- to- d ig it al c onve r te r ( a d c ) m o dule? fo r det aile d infor m ation. the t e m p eratur e of t he silicon die can be calcula t ed by the a d c measurement by using e quation 20-1 . a factor y-stor ed 10-bit ad c value for 3 0 c is locat ed at addre s s 2084 h. the temper atur e coe f f i cient for this circuit is 16 mv /c . other temper atur e r eadings can be calculated from the 30 c m ar k . equa tion 2 0 -1: s i l i c on die t e mp e rature adc mux v dd adc chs bi ts (adcon 0 reg i s t er) n v ou t temp_die( ? c ? a d c _rea ding (counts) ad c _30 ? c _re ading (c ou nts ? ?? 3.47 (counts/ ? c ? -- --- --- -- --- --- --- --- -- --- --- --- --- -- --- --- --- -- --- --- --- --- -- --- --- --- --- -- --- --- --- --- -- --- --- --- --- -- --- --- --- -- --- --- --- -- - -- --- --- --- --- -- --- - -3 0 ? c + = http:///
MCP19114/5 ds20005281a-page 124 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 125 mcp191 14/5 2 1 .0 analog-to-digit al conv erte r (a dc) module th e ana l og -to-d i git a l c onv ert e r (ad c ) a llo w s c onv ers i o n o f an an alo g i npu t s i g nal to a 1 0 -bi t bi na ry re pres en t a ti on o f t hat s i gn al. th is d e v i c e use s an alo g i npu t s , w h i c h are m u lti p l e xe d into a si ngl e s a m p le -an d -ho l d c i rc uit. th e out put of th e s a m p le -an d -ho l d is c onn ec ted to th e i npu t o f th e c onv ert e r . t he c o n v er ter ge ne rate s a 1 0 -b it bi na ry re su lt v i a suc c ess iv e a ppro x i m a t io n an d s t ore s th e ri ght j u s t ifi ed c onv ers i o n res u lt i n to th e ad c re su lt re gis t er s (adresh:adresl reg i s t er p a i r). fi gu re 21 -1 sh ow s th e bl oc k d ia g r am of t h e a d c . th e i n ter nal ban d ga p s upp li es t he v o l t ag e ref e ren c e to th e adc. figure 21-1: adc b l ock diagram gpa0/an0 vref ip_adj vbgr* ea_sc ov_ref v s chs 4: chs0 adc adon go/ done adresh adresl 10 10 v s s a2 reserved ip_off_ref v in/n gpa1/an1 gpa2/an2 gpa3/an3 gpb1/an4 (mcp19115 only) gpb4/an5 (mcp19115 only) gpb5/an6 (mcp19115 only) gpb6/an7 chs 4: chs0 v dr /n temp_sns pedestal dll_vcon slpcmp_ref av dd 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 11000 11001 11010 11011 11100 11101 11110 11111 tri-state reserved no te 1 : w hen ad o n = 0 , a l l mu l t i p le xe r in pu ts a r e di sc on n e c t ed . 2: r e fer t o ad c o n 0 reg i s ter fo r de t a i l ed ana l o g c h a nne l s e l e c t ion pe r de vi ce. http:///
MCP19114/5 ds20005281a-page 126 ? 2014 microchip technology inc. 21. 1 adc conf i gurat ion w hen c onf igu r ing a nd us ing th e ad c , th e foll ow in g fu nc tio n s mu st be c o n s i dere d : ? p o r t c onfi g u r ati o n ? c h ann el s el ec t io n ? a dc co nve r s i on clock s o u r ce ? i n t erru pt c o n t rol ? r e s ul t fo rma ttin g 21. 1.1 p ort configur ation th e ad c i s u s e d to co nve r t a nal og s i g nal s i nto a c orre sp ond ing di git al r epre s e nt at i on . wh en co nve r tin g a nal og si gna ls , t he i/o p i n sh oul d be co nfi gure d for a nal og b y s e tt ing the ass o c i a t ed tr is an d an sel b i t s . re fer to secti o n 1 8.0 ? i /o por t s ? for m o re in f o rm at i o n. 21. 1.2 cha nnel s e le ction th ere are u p t o 2 1 ch ann el se lect i ons a v a ila ble fo r th e m c p19 1 1 4 a nd 24 c h a nne ls for the mc p1 91 15: ? a n < 4 : 0> pi ns ? a n < 7 : 5> pi ns ( mc p 1 91 1 5 on ly ) ?v in : 1/1 5 .5 3 of the in put vo lt ag e (v in ) ?v re f : vo lt a ge refe renc e f o r re gul ati on s e t p o i n t ? o v _ r e f: r e fe r e nc e f o r ov co mpar a t or ?v bg r : ba nd g a p refe renc e ?v s : vo lt a ge p r op orti ona l to v ou t ? ea_ sc : erro r ampl ifi e r o u tp ut a f ter sl ope c o m pen sa tio n ? a 2 : s eco nd ary cu rrent se ns e am pl ifi er o utp ut ? pedest al ? r eser ved ? r eser ved ? i p_ adj : i p af ter p ed est al and of fse t ad ju st ? i p_ o ff_ref : i p o f fs et refe renc e ?v dr : v dr * 0 . 229 v/v ? te m p_ sn s : an alo g v o l t ag e re pre s en tin g i n te rnal te mp erat ure (refe r to equa tio n 20 -1 ) ? d l l_vc o n : d ela y l oc k e d lo op vo lt a ge r efere nc e ? s lp c m p _ r e f : sl o p e co mp en s a t i on r e f e r e n c e th e c h s <4: 0 > bi t s i n the ad c o n 0 re gis t er determ i n e w h ich c h a nne l is c onn ec ted to th e sa mp le a n d hol d ci r c u i t. w hen c h a ngi ng c h a nne ls , a de lay is re qu ired b e fo re s t art i ng th e n e xt co nv ersi on . r e fer t o se ction 2 1 . 2 ? a d c op er ati o n ? for m o r e in form at ion . 21. 1.3 a d c conve r s i on clock th e s o u r ce of the c onversi on c l oc k is s o f t w a re s ele ct abl e v i a t he ad c s b i t s in the ad c o n 1 r egi ste r . th ere are fiv e p os s ib le cl oc k o pti ons : ?f os c /8 ?f os c /16 ?f os c /32 ?f os c /64 ?f rc (c loc k deri v e d fr om int e rna l o s c ill ato r with a di vi so r of 16) th e tim e to co mp lete one -bi t con v e r si on i s de fin ed a s t ad . on e fu ll 1 0-bi t co nv ers i on requ ires 1 1 t ad pe r i o d s, as s how n in fig u re 21- 2 . fo r a co rrec t co nv ers i on , the app ropri a te t ad s pec if ica t io n m u s t be m e t . r e fe r to th e a/d c o nv ers i o n re qui rem ent s i n sec t ion 4 .0 ?ele ctric a l c h ar a c t er i s t i cs ? for m o re inf o rm ati on. ta b l e 2 1 - 1 gi ve s exa m p l es o f ap prop ria t e ad c c l o c k se le cti ons . note : an alo g v ol t ag es on a ny pi n t hat is d efin ed a s a d i gi t al in pu t m ay c aus e the in put b u f f e r to co nd uct ex ce ss cu r r e n t . note : u n le ss us in g t h e f rc , an y c h a n ge s in the sy st e m c l o c k f r e q u e nc y wi l l ch an g e t h e ad c c l o c k fre que nc y , w h i c h ma y ad ve rse l y af fec t th e ad c re su lt. t able 2 1 -1: adc clock p e ri o d (t ad ) vs . de vice ope rating freque ncie s adc clo c k pe riod ( t ad ) de v i c e frequ e nc y ( f os c ) adc clock source adcs<2:0> 8 mhz f osc /8 001 1.0 s ( 2 ) f os c /16 101 2. 0 s f os c /32 010 4. 0 s f os c /64 110 8.0 s ( 3 ) f rc x11 2.0 ? 6 . 0 s ( 1 , 4 ) le gen d : sh ade d c e ll s are o u t s id e o f re com m end ed rang e. note 1 : th e f rc s our ce has a typ i c a l t ad ti me of 4 s f o r v dd >3 . 0 v . 2: th es e v a lu es vi ol ate the mi nim u m re qui red t ad ti me . 3: fo r fa ste r c onv ers i o n ti me s, the se lec t i on of an othe r c l oc k so urce is re com m e nd ed. 4: th e f rc cl o ck s o urce is only recommended if the conversion will be performed during sleep. http:///
? 2014 microchip technology inc. ds20005281a-page 127 mcp191 14/5 figure 21-2: analog- to-dig it al conve r s i on t ad cyc l es 21. 1.4 inte rrup t s th e ad c mo du le a llo w s fo r t he a b il ity to g ene rate a n i n ter r upt upo n c o m p l e tio n o f an an alo g -to - dig i t a l c onv ers i o n . the ad c i n ter r upt fla g is th e ad if bi t i n th e pir1 re gis ter . the adc in terru pt ena b le is th e adie b i t i n the pie1 re gis t er . the adif bi t mu st b e cl ea r e d i n s o ft w a r e . th is i n te rrup t ca n be g ene rate d w h il e th e dev ic e i s op era t in g or w h i l e i n slee p. if t he de vi ce i s i n slee p, th e i nterr upt w i l l w a ke up t he dev ic e. u po n w a ki ng from sl eep , t he ne xt in structi o n fo llo w i ng th e sleep in s t r u ct i o n is a l w ay s ex ec ut e d . i f t he us er is a t t em pt i ng t o w a k e u p f r om s l ee p an d r e s u m e in - l i n e co de ex ec uti o n , th e g i e and peie bi t s in the in tc o n re gis t er m u s t be dis a b l ed . if th e g i e and peie bi t s i n th e in t c on regi ste r are en ab led , ex ec uti on w ill s w itc h to the int e rrup t se rvi c e routi n e . 21. 1.5 r e s ul t fo rm atting th e 10-b i t a/d c onversi o n r e su lt is s upp lie d in rig h t j u st ifi ed f o rm at o n ly . figure 21-3: 10-bit a/d re sult form at t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit h o l d in g c apa ci t o r i s di s c o n n e c t e d f r om an al o g i n pu t ( t y p i c a l ly 10 0 n s) t ad 9 t ad 10 t cy - t ad adresh:adresl i s l oad ed , g o b i t is cl eare d , adif bit is set, holding capacitor is connected to analog input. c o nv ers i on st art s b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: note 1: the adif bit is set at th e com p l e ti on of ev e r y co nv e r s i on , r e g a r d l e s s of w h et h e r o r no t the ad c in terru pt i s ena ble d . 2: th e ad c ope rate s du ring slee p on ly w h e n t he f rc o s c i l l ato r is s e le ct ed. (adfm = 1 ) ms b l s b bit 7 bit 0 b it 7 b it 0 r e ad as ? 0 1 0 -b i t a/d re s u l t http:///
MCP19114/5 ds20005281a-page 128 ? 2014 microchip technology inc. 21. 2 adc oper ati o n 21. 2.1 s t a rting a conve r si o n t o en ab le th e ad c mo du le, t he ad o n bit in t h e ad c o n 0 reg i s t er m u s t be s e t to a ? 1 ? . setti ng th e go/ don e b i t in t he adco n0 reg i s t er to a ? 1 ? w i l l st art th e a nal og- to-di gi t al co nv ersi on. 21. 2.2 c o m p l e t i o n of a co nv er sio n w hen the co nv ers i on is co mp let e , th e ad c m o d u le w i l l : ? c l ear t he go /d o n e bi t ? s e t th e adif inte rrup t fla g b i t ? up date the ad r e sh : a d r esl reg i s t ers w i th new c onv ers i o n re su lt 21. 2.3 t e r m i natin g a conv er sion i f a co nv e r si on mu st b e t e r m in a t ed be f o r e co mp l e t i on , th e g o /do n e bit c an be c l ea red i n s o f t w a re. th e ad r esh :ad r esl reg i st ers w ill no t be up date d w i th th e p a r tia lly com p l e te a nal og -to-d i gi t a l c o n v er sio n s a m p le . ins t ea d, th e adresh:adresl reg i s t er p a i r w i ll ret ain t he v alu e of the p r ev io us c onv ers i o n. ad dit i on all y , tw o ad c cl oc k c y c l e s a r e re qui red b e fo re a noth er acquis iti on c an b e in itia ted . fol l ow i ng th e d e la y , an i npu t ac qui si tio n is aut om atic al ly st a r ted o n th e s e l e ct ed cha n n e l. 21. 2.4 a dc ope r ation during s l e e p th e ad c i s n o t o pera t io nal dur ing slee p m o d e . th e v av d d 4 v re fere nc e h as b een re mo ve d t o mi nim i z e sl eep cu rren t . 21. 2.5 a /d conv ers i on p r o c edur e th is i s an ex am pl e proc ed ure for us in g the ad c to pe rfor m a n a nal og-t o-di git al con v e r si on: 1. c o n f ig ure port: ? d is abl e p i n outp u t driv er (r efer to t he t r isgp x re gis t ers ) ? c onf igu r e pi n as ana log (re fer to the an sel x r e gi ste r s) 2. c on f ig ure the ad c mo dul e: ? s el e c t a d c co nv er s i o n cl oc k ? s e l ec t ad c i npu t c han ne l ? t ur n on a d c mo du l e 3. c o n f ig ure ad c int e rrup t (o ptio na l): ? c lea r adc in terru pt flag ? e na ble ad c in terru pt ? e na ble pe riph eral in terru pt ? e na ble gl oba l i n terr upt ( 1 ) 4. w a it th e re qui red ac qui si tio n ti me ( 2 ) . 5. s t art co nv ers i on by se tti ng t he go /d o n e bi t. 6. w a it for ad c c o n v ers i on to complete by one of the following: ? polling the go/done bi t ? w ait i ng for the ad c int e rrup t (i nter rupt s en abl ed) 7 . re a d adc re s u l t . 8. cle a r th e adc int e rrup t fla g (re qui red i f in terru pt i s e nab led ) . ex amp l e 21-1: a/d c o n v e r sion note : th e go/do ne b i t s hou ld n o t b e se t in the s a m e ins t ru cti on tha t turn s on the ad c . re f e r to secti o n 2 1.2. 5 ? a /d c o n ver s i on pr o cedu r e? . note : a device reset forces a l l re gis t er s to th eir r e s e t s t ate . th us , th e ad c mo dul e is tu rne d o f f and an y pen din g c o n v e r si on is te rmi n a t ed. note 1 : th e g l o bal in terru pt can be d i sa bl ed if the us er i s a ttem p ti ng to wak e up from sle e p an d re su me in -lin e c od e ex ec uti on . 2: re f e r to se ction 2 1 . 4 ? a /d ac quis i tion r e q u ir em ent s ? . ; thi s cod e b lo ck co nfi gur es th e adc ; for p oll ing , frc c loc k a nd an 0 inp ut . ; ; con ve rsi on st art & po lli ng fo r com pl eti on ; a re in clu ded . ; b ank se lad con 1 ; m ovl wb ?01 110 00 0? ; fr c c loc k m ovw fa dco n1 ; b ank se ltr isg pa ; b sf t ris gp a,0 ;se t gpa 0 to inp ut b ank se lan sel a ; b sf a nse la ,0 ; set g pa0 t o a nal og b ank se lad con 0 ; m ovl wb ?01 100 00 1? ; se lec t c ha nne l an0 m ovw fa dco n0 ; tu rn ad c o n c all s amp le tim e;a cq uis it on del ay b sf a dco n0 ,1 ; sta rt co nv ers ion b tfs ca dco n0, 1 ; is co nve rsi on do ne ? g oto $ -1 ; no, t est ag ai n b ank se lad res h ; m ovf a dre sh ,w ; rea d upp er 2 bit s m ovw fr esu lth i ; sto re in gp r spa ce b ank se lad res l ; m ovf a dre sl ,w ; rea d low er 8 bit s m ovw fr esu ltl o ; sto re in gp r spa ce http:///
? 2014 microchip technology inc. ds20005281a-page 129 mcp191 14/5 21. 3 adc regi st er defi nit i on s th e fol l ow i ng reg i st ers ar e u s e d to con t rol th e op e r at i on of t h e a d c : regis t er 21-1: adcon0: a/ d control re g i ste r 0 u-0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 ? chs4 chs3 chs2 chs1 chs0 go/done ad o n bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 6- 2 c h s< 4:0> : ana l og c h a nne l se lec t b i t s 00000 = v in / n an alo g v o lt age m eas ure m e n t (v in /n =v in /1 5.5 328 ) 00001 = vr ef (d ac ref e ren c e vo lt a ge set t in g c u rren t re gul ati on l e v e l) 00010 = o v _ r ef (ref e ren c e for ov ervo lt a ge co mp arat or) 00011 = vb gr (b and ga p re fere nc e) 00100 = v s (v ol t a g e p r opo rtio nal to v ou t ) 00101 = ea _sc (erro r am p a f ter slop e c o mp ens ati o n out put) 00110 = a2 (sec on dar y c u rrent sens e amp lifi e r o u tp ut) 00111 = pe d e st al (ped es t a l v o l t ag e) 01000 = rese r ved 01001 = rese r ved 01010 = i p _ad j (ip a f ter pede st a l a nd of fs et ad jus t (a t pwm c o m p arato r)) 01011 = ip _ o f f _ r e f ( i p of f s et r e fe r e nc e) 01100 = v dr /n (v dr / n an alo g d r iv er v o l t ag e m eas ure m e n t = 0.2 29v/ v * v dr ) 01101 = t e mp_ s n s (an a lo g v o l t ag e rep r es en ting in tern al tem pera t ure ) 01110 = d l l_vc o n (d e l ay lo ck ed -loo p v o lt a ge r e fere nc e ? c ont rol vol t ag e f o r de ad tim e ) 01111 = sl pc mp_ r ef (sl ope co mp en sat i on refe ren c e) 10000 = u ni m p l em en t ed 10001 = u ni m p l em en t ed 10010 = u ni m p l em en t ed 10011 = u ni m p l em en t ed 10100 = u ni m p l em en t ed 10101 = u ni m p l em en t ed 10110 = u ni m p l em en t ed 10111 = u ni m p l em en t ed 11000 = gpa0/an0 (i.e. addr1) 11001 = gpa1/an1 (i.e. addr0) 11010 = g p a2/an2 (i.e . t e m pera t ure sen s o r inp u t) 11011 = g p a3/an3 (i.e . bin) 11100 = gpb1 /an4 11101 = g pb4 /an5 ( mcp 1 91 1 5 on ly ) 11110 = g pb5 /an6 ( mcp 1 91 1 5 on ly ) 11111 = g pb6 /an7 ( mcp 1 91 1 5 on ly ) bi t 1 go / d o n e : a/d c o nv ersi on s t atu s b i t 1 = a /d co nv ers i on cy c l e i n p r ogr ess . se ttin g t h is bi t s t art s a n a/d c o n v e r si on cy cl e. thi s b i t i s a u to ma tic a l l y cl eare d b y h a rdwa re wh en t he a/d co nv ers i on ha s c o m p l e ted . 0 = a /d co nv ers i on co mp let ed/ not in prog res s bi t 0 ad o n : ad c en abl e b i t 1 = a d c is ena ble d 0 = a d c is dis a b l ed an d c onsum es no op erat ing cu rren t http:///
MCP19114/5 ds20005281a-page 130 ? 2014 microchip technology inc. regis t er 21-2: adcon1: a/ d control re g i ste r 1 u-0 r / w -0 r/w - 0 r / w -0 u-0 u -0 u-0 u -0 ? adcs2 adcs1 adcs0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 6- 4 a d c s <2 : 0 >: a/d c o n v e r si on c l oc k sele ct bit s 000 =r es erv e d 001 =f os c /8 010 =f os c /32 x11 =f rc (c loc k deri v e d fr om int e rna l o s c ill ato r w i th a div i s o r o f 16 ) 100 =r es erv e d 101 =f os c /16 110 =f os c /64 bi t 3- 0 u n i m pl e m en t e d: re a d a s ? 0 ? regis t er 21-3: adre sh: ad c re sult re giste r high u-0 u-0 u-0 u-0 u-0 u-0 r-x r-x ? ? ? ? ? ? a d r es 9 a dres8 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1- 0 a d r es< 9:8> : m o s t sig n if ic ant a/d r e s u lt s regis t er 21-4: adre sl: adc res u lt re g i ste r low r-x r -x r-x r -x r-x r -x r-x r -x adres7 adres6 adr e s 5 adres4 adres3 a d res2 ad res 1 adres0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bit 7-0 adres<7:0> : least significant a/d results http:///
? 2014 microchip technology inc. ds20005281a-page 131 mcp191 14/5 21. 4 a / d acqui sit i o n requi rement s fo r th e ad c to me et i t s s p e c i f ie d ac cu rac y , th e c harg e h o ld ing c a p a ci tor (c ho ld ) mu st be a l lo w e d t o f u l l y c har ge to th e in put c han nel vol t ag e le vel . the an alo g in put mo del is sho w n in fig u re 21-4 . th e so urc e i m p eda nc e (r s ) and th e i n te rnal s a m p li ng sw i t ch (r ss ) i m p eda nc e di rec t ly af fec t the tim e re qui red to c harg e t h e c apac it o r c ho ld . t he s a m p li ng s w itc h (r ss ) i m p eda nc e v a rie s ov er th e d e v i c e v o lt age (v dd ), re fer to fi gure 2 1 - 4 . th e ma xi m u m r e co m m e n de d im ped a nc e for a n al og s ource s is 10 k ? . as t he s ourc e im pe dan ce i s de cre as ed, th e ac qu isi t io n ti me ma y be dec rea s e d. af t er the ana lo g in put c ha nne l is selected (o r cha nge d), an a/ d a c qu is iti on m u s t b e do ne bef ore t he c o n v er sio n c a n be s t ar ted. t o ca lcu l a t e th e m i n i m u m ac qui si tion ti me, e q ua t i on 21 - 1 ma y b e us ed . th is equ ati on as sume s th at 1 / 2 l s b e rror i s u s e d ( 1 , 0 2 4 s t eps f o r t h e a d c ) . t h e 1/ 2 l s b e r r o r is t h e m a x i m u m e rror all o wed f o r the adc to m e et it s s pec if ied res olu tio n. equa tion 2 1 -1: acquis i tion t i me ex amp l e note 1 : th e c h a r ge hol din g c a p a ci tor (c ho ld ) i s not disc h a rg ed a f te r ea ch co nve r si on. 2: th e m ax i m um rec om m end ed i m p ed anc e f or an al og s ou r ce s i s 1 0 k ? . thi s is requ ire d to me et the pin l eak ag e s pec ifi c a t io n. t acq amplifier settling time hold cap a ci to r ch a r g i n g time t e m p er a t u r e c o e f ficien t ++ = t amp t c t co ff ++ = 2 s t c te m p era t ure - 25 c ?? 0.0 5 s / c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln (1 /2 0 4 7 ) ? = 10 pf 1 k ? 7 k ? 10 k ? ++ ?? ? l n ( 0 .0 004 885 ) = 1.3 7 = s v appli e d 1e t c ? rc -- -- -- -- - - ? ?? ?? ?? ?? ?? v appli e d 1 1 2 n1 + ?? 1 ? - -- -- -- --- -- -- -- -- -- -- -- --- -- - ? ?? ?? ?? = v appli e d 1 1 2 n1 + ?? 1 ? - -- -- --- -- -- -- -- -- -- -- --- -- -- - ? ?? ?? ?? v ch old = v appli e d 1e t c ? rc -- -- -- -- - - ? ?? ?? ?? ?? ?? v ch old = ;[1 ] v ch o l d ch ar ged t o w i t h in 1/ 2 l s b ; [2 ] v ch o l d ch ar g e r e s pon se t o v app l i ed ; c om b i ni ng [ 1 ] a n d [ 2 ] th e value f o r t c ca n b e a p p r o x i m a t ed w ith th e fo llo win g eq u a t i o n s: s o lvin g fo r t c : ther efor e: t e m p e r a t u r e + 50 c and ext ern a l i m peda nce o f 10 k ? 5. 0 v v dd = as su mp ti o n s : no t e : wher e n = n u mber o f bits o f the adc . t acq 2 s 1. 37 s 50 c - 2 5 c ?? 0.0 5 s / c ?? ?? ++ = 4.6 7 s = http:///
MCP19114/5 ds20005281a-page 132 ? 2014 microchip technology inc. figure 21-4: analog inp u t mode l figure 21-5: adc t rans fer fun c tion c pin va r s an alo g 5 p f v dd v t ? 0.6 v v t ? 0. 6v r ic ? 1k ss r ss c ho l d = 10 pf v ss /v re f - 6v sa m p lin g swi t c h 5v 4v 3v 2v 567 8 9 1 0 1 1 (k w) v dd r ss note 1: refer to section 4.0 ?electrical characteristics? . inp u t pin sam p l i ng swit c h i l eakag e ( 1 ) le gend : c ho ld = s am pl e / h o l d c a pac ita n c e c pi n = i n put ca p a c i t an ce i l eakag e = l eak ag e cu rren t at th e pi n d ue to va riou s j unc tio ns r ic = i nt e r co nn e c t re si stan c e r ss = r es is t a nce of sam p li ng sw itc h ss = s a m p lin g swi t c h v t = t h r es hol d v o lt a g e 3f fh 3feh adc o utput code 3fd h 3f c h 03 h 02 h 01 h 00 h f ull -sca le 3fbh 0.5 lsb v re f - zero-sca le t r an sit ion v re f + t r ans iti o n 1.5 ls b full-sc a le r ang e ana l og inp u t v o lt age http:///
? 2014 microchip technology inc. ds20005281a-page 133 mcp191 14/5 t able 2 1 -2: s um mar y of re giste r s ass o ciated wi t h adc nam e bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 re g i s t e r on page adcon0 ? chs4 chs3 chs2 chs1 chs0 go/done ado n 129 adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? 130 adresh ? ? ? ? ? ? a dres9 adres8 130 adresl adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 130 ansela ? ? ? ? a nsa3 ansa2 ansa1 ansa0 11 2 anselb ? ? ansb5 ansb4 ? ansb2 ansb1 ? 11 7 intcon gie peie t0ie inte ioce t0if intf io cf 93 pie1 ?adie bclie sspie cc2ie cc1ie tmr2ie tm r1ie 94 pir1 ?adif bclif sspif cc2if cc1if tmr2if tm r1if 96 trisgpa trisa7 trisa6 trisa5 ? t risa3 trisa2 t r i sa1 trisa0 111 trisgpb trisb7 trisb6 trisb5 trisb4 ? ? trisb1 trisb0 11 6 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for adc module. http:///
MCP19114/5 ds20005281a-page 134 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 135 mcp191 14/5 22 .0 t i me r0 m o du le t h e t i m e r 0 mo du le is an 8- b i t t i me r / c o u n t er w i th t h e fo ll ow in g fe atur es: ? 8 -b it tim e r/c o u n te r reg i s t er (t m r 0 ) ? 8 -b it pres c a le r ? p ro gram m abl e i n te rnal or e x t e rna l c l o c k so urc e ? p ro gram m abl e e x te rna l c l oc k edg e s e le ct ion ? i nt e r r up t on ov er f l ow fi gu re 22 -1 i s a bl oc k d i a g ram of the t i m e r0 mo dul e. f i g ure 22- 1: t i me r 0 block di agram 22. 1 t imer 0 opera t i o n th e t i me r0 mo dul e c an be us ed as ei the r an 8-b i t tim er o r an 8-bi t c oun ter . 22. 1.1 8 - b i t t i mer mo de th e t i me r0 mo dul e w i ll inc r em en t e v e r y i n s t ruc t io n c y c l e , i f u s ed w i thou t a pr esc a l e r . 8-bit t i me r m ode i s s e l e ct ed b y c l e a rin g th e t0 c s bit in t he o p tio n _r eg re gis t er . w hen tm r 0 is w r i tten , t he in crem en t i s in hib i te d for tw o in stru cti o n cy cl es im me di atel y foll ow in g t he w r i t e. 22. 1.2 8 -bi t counter mode in 8 - bit c ounter mode, t he t i mer0 modu le w ill incr em e nt on ever y rising or falling edge of the t0 c k i pin. t he increment ing edge is det ermined by th e t0se bit in t he o p tion _r e g register . 8-b i t c ounter mode usin g the t0c k i pi n is selected by setting the t0 c s bit in the opti o n _r e g r egister to ? 1 ?. 22. 1.3 s o f t w a r e pr og ra mm ab le pr es cal e r a s i ng le sof t w a re prog ram m a b le pres c a le r is av ail a bl e fo r u s e w i t h eith er t i m e r0 or th e w a tc hdo g t i m e r (wd t ), bu t not both si mu lt a neo us ly . th e pre s c a l e r as s i gn m e nt i s c ont roll ed b y t he psa b i t i n th e o p tio n _r eg regi ste r . t o a s s i gn t he pre s c a l e r to t i m e r 0 , th e psa bit m u s t be cl e a re d to ? 0 ?. th ere are eig h t p r es ca ler opt ion s f o r th e t i me r0 m odu le rang ing from 1: 2 to 1:2 56. the pres ca le val u e s ar e s e le ct abl e v i a the ps<2: 0> bit s i n th e o p tio n _r eg re gis t er . in orde r to hav e a 1: 1 pre s c a l e r v alu e for the t i me r0 mo dul e, the p r es ca ler m u s t b e di s a bl ed by s e tt ing t he psa bit i n the option_reg re gis t er . the prescal er is not readabl e or w r it able. when as signed to the t i m er 0 modul e, all i nstructions w r i t i ng to the tm r 0 regis t er w ill c l ear the presc a ler . t0cki tmr0se tmr0 ps<2:0> data bu s set fla g b i t tm r0i f on ov erfl ow tmr0 cs 0 1 0 1 8 8 8-bi t pres c a ler f os c /4 psa sync 2 t cy o v e r flo w to t i me r1 note : th e v a lu e w r i tten to the tmr 0 re gis t er c an be a d ju ste d , i n o r der to ac c oun t for th e tw o in st ruc t ion cy cl e del ay w h en tmr0 i s wri tte n . http:///
MCP19114/5 ds20005281a-page 136 ? 2014 microchip technology inc. 22. 1.4 s w i t chin g pre s ca le r be twe e n t i me r0 a nd w d t modul es a s a r e sul t o f hav ing t he pr esc ale r assi gn ed to ei th er t i me r0 or th e w d t , it i s p o ssi bl e t o ge ner a t e an un int e n d e d d e vi ce r e set wh en swit chi n g pr es cal e r val u e s . wh en ch an gin g th e p r esca le r ass i g n me nt f r o m t i me r0 t o t he w d t mod ule , th e ins t r uc t i on se que nce sho w n in e x am ple 22- 1 m u st be exe c ut ed . ex amp l e 22-1: changing p r e s cale r (t im er0 ? wdt ) wh en ch ang in g th e p r esca le r as sig n me nt f r o m t h e w d t t o th e t i m e r0 m o du le , t h e fo ll ow i n g i n s t r u c t i o n s e qu en c e m u s t be e x ec u t e d ( r efe r to e x am pl e 2 2 - 2 ). ex amp l e 22-2: changing p r e s cale r (w dt ? tim e r0 ) 22. 1.5 t ime r 0 i n t e rru pt t i mer 0 w i ll ge ner ate an i nter r upt w he n the tm r 0 re gis t er o v e r flo w s from ffh to 00 h. th e t0 if in terru pt fl ag bit in t he in tc o n regi st er is s e t e v e r y t i m e th e tm r 0 re gi ste r ov erfl ow s, reg a rdl e s s o f w h e t her or n o t th e t i m e r0 in terru pt is en abl ed . th e t0if b i t ca n o n l y be c l ea red in s o f t wa re. the t i m e r0 in terru pt ena b le i s th e t0 ie b i t i n th e int c o n re gi ste r . 22. 1.6 u s i ng t i me r0 w i t h a n ex t e r n al clo c k w h e n t im e r 0 i s in c o un t e r mo de , t he syn chr oniza tio n of t he t 0 c k i in put a nd th e t i me r0 r egi ster is acco mplish ed by samp ling t he pr escal e r ou tpu t on th e q2 and q4 cycles of t he int e r nal pha se clocks. th ere f ore, th e h i gh an d low periods o f th e e x t e rna l cl o ck s o u r ce mu st me et t h e t i m i n g r e qu i r em en ts as s how n in sec t ion 4 .0 ? e le ctrica l cha r acte r istic s ? . 22. 1.7 o pe rati o n during s l e e p t i mer 0 c ann ot o pera t e w h ile the proc es so r is in slee p m ode . the c onten t s o f the tm r 0 regi ste r w i ll rem a i n un ch ang ed w hil e th e p r oc es sor is in sle ep m od e. bankseltmr0; clrwdt ;clear wdt clrftmr0;clear tmr0 and ;prescaler bankseloption_reg; bsf option_reg,psa;select wdt clrwdt ; ; movlwb?11111000?;mask prescaler andwfoption_reg,w;bits iorlwb?00000101?;set wdt pre scaler movwfoption_reg;to 1:32 clrwdt ;clear wdt and ;prescaler bankseloption_reg; movlwb?11110000?;mask tmr0 select a nd andwfoption_reg,w;prescaler bits iorlwb?00000011?;set prescale to 1: 16 movwfoption_reg; note : the ti me r0 i n te rrupt ca nno t w a k e the pr oce s s o r from s l ee p s i n c e th e t i m e r i s f r oz en du r i ng s l e e p. t a ble 2 2 -1: s um mar y of re giste r s ass ociated wi t h t i m e r0 name bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b i t 1 b i t 0 re g i s t e r on page int c o n g i e p eie t 0 i e inte io ci e t0if intf iocif 93 option_reg ra pu intedg t0cs t 0 se psa ps2 ps1 ps0 76 tm r 0 t i me r0 m odu le r egi ste r 13 5 * trisgpa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 t r isa0 111 le gen d : ? = u n i m p l em en ted loc a tions, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information. http:///
? 2014 microchip technology inc. ds20005281a-page 137 mcp191 14/5 2 3 .0 t i mer1 m o du le w i th gate control th e t i m e r1 mo dul e is a 16 -bi t tim e r w i t h the foll ow in g fe atu r es : ? 16-bi t ti m e r reg i s t er p a ir (tm r 1 h :tm r 1l) ? r ea da ble an d w r it a b le (bo t h r egi ste r s) ? s el e c ta bl e i n te r n al cl oc k s o u r ce ? 2 -bit pres c a le r ? i nt e r r up t on ov er f l ow fi gu re 23 -1 i s a bl oc k d i a g ram of the t i m e r1 mo dul e. figure 23-1: t i m e r 1 block dia g r am 23. 1 t imer 1 opera t i o n th e t i me r1 mo dul e i s a 16 -bi t in cre m e n ti ng tim e r w h ic h i s ac ce ss ed t hrou gh th e tm r 1h : tm r 1l regi ste r p ai r . w r i t es t o t m r 1 h or t m r 1 l d ir e ct l y up da t e t h e c oun ter . t he tim e r is i n c r em ent ed on ev ery i n s t ruct io n cy cl e. t i me r1 i s e nab led by c onf igu r in g th e tm r 1 o n b i t i n th e t1 c o n regi st er . t a b l e 23-1 di sp lay s the t i m er1 en abl e se le c t i o ns . 23. 2 c l o ck sour ce select io n the tmr 1c s bit in the t1c o n r eg i ster is used to s elect the clock sou r c e for t i me r 1. ta b l e 2 3 - 1 dis p lays the c l ock s our ce sele ctions. 23. 2.1 i nte rnal clock sour ce the tm r 1 h : tm r 1l regi ster p a ir w ill inc r em ent on m u ltiples of f os c or f os c /4 as dete r m i ned by the ti m e r 1 p r e s c a l e r . as an exa m ple, w hen the f os c i n ter nal cl ock sour ce is se lected, the t i mer1 regis t er valu e w ill inc r ement b y four co unt s every instruction c lock c ycle . tmr1h tmr1l tmr1cs t1ckps<1:0> 1 0 2 set flag b i t tm r 1 if o n o v erfl ow tmr1on note 1: tmr1 register i n c r em ent s o n ri si ng edg e. f os c tm r 1 ( 1 ) pre s c a l e r 1 , 2, 4, 8 t able 2 3 -1: c lock s o u rce s e l e ctions tm r1 cs cloc k sou r c e 1 8 m hz sy st e m cl o c k ( f os c ) 0 2 m h z in str u ct ion cl oc k ( f os c /4) http:///
MCP19114/5 ds20005281a-page 138 ? 2014 microchip technology inc. 23. 3 t imer 1 pr escale r t i me r 1 has four pres caler option s allow i ng 1, 2, 4 or 8 div i sion s of the cloc k in put. the t1c kps bit s i n the t 1 c o n r e gi st e r control the p r es cale coun t e r . the pres cale c ounter is not direc t ly readab le or w r it able; how ev er , the pres caler counter is cl eared upon a w r ite to tm r 1 h or tmr 1l. 23. 4 t imer 1 i n ter r upt th e t i m e r1 reg i st er p a i r (tm r 1h :t mr 1 l ) i n c r em ent s to fff fh a n d roll s ove r to 00 00h . wh en t i me r1 r o ll s o v er , th e t i m e r1 int e rrup t f l ag bi t i n the pir 1 regi ste r i s s e t. t o en abl e th e i n te rrupt on roll ov er , yo u m u s t s e t th es e b i t s : ? t m r 1o n b i t i n th e t1 c o n regi ste r ? t m r 1i e bit in the pie1 regi ste r ? peie bit in the intco n reg i s ter ? g ie b i t i n the i n tco n regi ste r th e i n terr upt i s c l e a red by c l e a ri ng th e tm r 1 if bit i n th e in terru pt serv ice rou t in e. 23. 5 t imer1 i n sl eep u n l i k e ot her st a nda rd m i d -rang e t i mer 1 m odu les, th e m c p191 1 4 /5 t i me r1 mo dul e onl y cl oc ks from a n i n tern al sy st em cl oc k, a nd thu s c a n not run duri ng slee p m ode nor c a n i t be u s e d to w a ke t he de vi ce from thi s m ode . 23. 6 t imer1 cont rol regi ster th e t i m e r1 c ontr o l (t1 c on ) re gi ste r , sh ow n i n r e gi st e r 23 - 1 , i s us ed to c o n t rol t i mer 1 and s e le ct th e va r i ou s f e at u r es of t h e t i m e r 1 mo du l e . note : th e tm r 1 h : tm r 1 l regi ste r p a i r and the tm r 1 i f bit sho u l d be c l e a re d be fore e nab lin g i nte rrupt s. regis t er 23-1: t1con: t i mer 1 control re g i ste r u-0 u -0 r/w-0 r/w-0 u-0 u-0 r/w-0/ r/w-0 ? ? t1ckps1 t1ckps0 ? ?t m r 1 c s t m r 1 o n bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 6 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 5- 4 t1ckps<1 : 0>: t i me r 1 i n p u t cl oc k p r es ca l e s e le ct b i ts 11 = 1 :8 p r es ca l e va l u e 10 = 1 :4 p r es ca l e va l u e 01 = 1 :2 p r es ca l e va l u e 00 = 1 :1 p r es ca l e va l u e bi t 3- 2 u n i m pl e m en t e d: re a d a s ? 0 ? bi t 1 tm r1 cs: t i m e r1 c l oc k sour ce c ontr o l b i t 1 = 8 mhz sy st em cl oc k ( f os c ) 0 = 2 mhz in st r u ct i o n cl o ck ( f os c / 4 ) bi t 0 tm r 1 o n : ti m e r 1 o n b i t 1 = e nab les t i m er 1 0 = s to p s t i m e r1 , cle a rs t i m e r1 gat e fl ip-f lop http:///
? 2014 microchip technology inc. ds20005281a-page 139 mcp191 14/5 t able 2 3 -2: s um mar y of re giste r s ass o ciated wi t h t i m e r1 nam e bit 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 r e gist er on pag e i n t c on gi e pei e t0ie inte ioce t0if intf io cf 93 pie1 ? adie bclie sspie cc2ie cc1ie tm r2ie tm r1ie 94 pir1 ? adif bclif sspif cc2if cc1if tm r2if tm r1if 96 tm r 1 h h o l di ng r egi ste r fo r the mo st sig n ifi c a n t by te of t he 16-b i t t m r 1 r egi ste r 137 * tm r 1 l h ol din g r e g i s t er f o r th e l eas t si gni fic a n t by te o f th e 16 -bi t tm r 1 r e gis t er 137 * t1con ? ? t1ckps1 t1ckps0 ? ? t m r 1c s t mr 1on 13 8 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. * page provides register information. http:///
MCP19114/5 ds20005281a-page 140 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 141 mcp191 14/5 24 .0 t i me r2 m o du le th e t i m e r2 mo dul e is an 8 - bi t tim e r w i t h the foll ow in g fe atu r es : ? 8 -bit tim e r r egi s t e r (tm r 2) ? 8 -bit peri o d reg i s t er (pr2 ) ? in terru pt o n t m r2 ma tch with pr2 ? s o f tw are pro g ram m abl e p r es ca ler ( 1 :1, 1:4 , 1: 16) re fer to fi gure 2 4 - 1 fo r a blo c k di agra m of t i me r2. 24. 1 t imer 2 opera t i o n th e cl oc k in put to th e t i m e r2 m o d u le i s the s y s t e m cl oc k ( f os c ). th e cl oc k is fed i nto the t i me r2 pre s c ale r , w h ich h as p r es cal e opt ion s of 1: 1, 1:4 o r 1 : 16. th e ou t p ut of t h e p r es ca l e r i s t h e n us ed t o i n c r em en t t h e tm r 2 regi ste r . th e val u e s o f t m r 2 and pr 2 are co ns t a n t ly c o m p are d to de term in e w h e n t hey m a tc h. t m r 2 w ill in cre m e n t fro m 0 0h un til i t ma tch e s t he v a lu e in pr 2 . whe n a m a tc h o c c u rs , tm r 2 is res e t t o 00 h on the nex t i n c r em ent cy cl e. th e m a t c h out put of the t i m e r2 /pr 2 com p a r ato r i s us ed to se t th e t m r2i f i n terr upt fla g b i t i n t he pir1 re gis t er . th e tm r 2 and pr 2 re gis t ers a r e bo th full y r ead abl e an d w r it a b le . o n any r e se t, th e tmr 2 reg i s t er is s e t to 00 h a nd the pr 2 re gis t er is se t to ffh . t i mer 2 is tu rned on by se tting th e t m r2o n b i t i n th e t2 co n re g i ste r to a ? 1 ?. t i m e r2 i s turn ed of f by c l e a rin g th e tm r2o n b i t to a ? 0 ?. th e t i m e r2 pre s c a le r i s c o ntro lle d by th e t 2 ckps bit s in t h e t 2 c o n r e gi s t e r . th e pr e s ca le r co u n t e r ar e c l ea red w hen : ? a wri t e t o tmr2 o c cu rs. ? a wri t e t o t2 co n o c cu rs. ? a n y dev ic e res e t oc cur s (pow er-on r e s e t, mc l r reset, watchdog timer reset, or brown-out reset). figure 24-1: timer2 block dia g r am note : tm r 2 i s no t c l ea red w h en t 2 c o n i s wri t te n . c o mp ara t or tmr2 se t s fla g tmr 2 ou t p u t re s e t pres c a ler pr2 2 f os c 1:1, 1:4 , 1: 8, 1 : 16 eq b i t t m r2 if t2ckps<1:0> http:///
MCP19114/5 ds20005281a-page 142 ? 2014 microchip technology inc. 24. 2 t imer 2 cont rol regi ste r regis t er 24-1: t2con: t i mer 2 control re g i ste r u-0 u -0 u-0 u -0 u-0 r /w -0 r/w -0 r /w -0 ? ? ? ? ? t m r 2on t 2 c kps1 t 2 ckps1 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 3 u n i m pl e m en t e d: rea d as ? 0 ? bi t 2 tmr2 o n : ti m e r 2 o n b i t 1 = t im er2 i s on 0 = t im er2 i s of f bi t 1- 0 t2ckps<1 : 0>: t i m e r2 c l oc k p r esc a l e se lec t b i t s 00 =pre sc ale r is 1 01 =pre sc ale r is 4 10 =pre sc ale r is 8 11 =pre sc ale r is 16 t a ble 2 4 -1: s um mar y of re giste r s ass o ciated with t i mer 2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 r e gi ster on pa ge int c on g i e peie t0ie inte ioce t0if intf iocf 93 pie1 ? adie bclie sspie cc2ie cc1ie tmr2ie tmr1ie 94 pir1 ? adif bclif sspif cc2if cc1if tmr2if tm r 1 if 96 pr 2 t i m e r 2 m o d u le peri od r egi ste r 14 1 * t2con ? ? ? ? ? tm r2on t2ckps1 t2ckps0 142 tm r2 hold ing reg i st er fo r th e 8-b i t tmr2 t i m e ba se 14 1 * legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for timer2 module. * page provides register information. http:///
? 2014 microchip technology inc. ds20005281a-page 143 mcp191 14/5 25 .0 e nhance d p w m module th e pwm m odu le imp l em en ted o n th e mc p1 91 14 /5 i s a sc al e d - d o w n ve r s i o n o f t h e c a pt u r e/ c o mpar e / p w m (c c p ) mo dul e fo un d i n s t an da rd m i d -rang e m i c r oc ont roll ers . the mo dul e onl y fe atu r es t he pw m m odul e, w h ic h i s s l i ghtl y m o d i fi ed f r om st a nda rd m i d -rang e m i c r oco n tro l l e rs . in th e mcp1 91 14 /5, th e pw m m odu le is us ed to g ene rate t he s y s t em cl ock or sy st e m o sci l l a t or . t h i s sys t e m cl oc k c a n co n t r o l t h e m c p19 1 1 4 /5 s w it chi n g f r equ enc y , as w e ll as s e t th e m a x im u m a llo w abl e dut y cy cl e. the pw m mo dul e d oes no t c on t inu ous ly a dju st the du ty c y c l e to co ntro l th e o u tp ut vo lt ag e. thi s is ac co mp lis he d b y the an alo g c ont rol loo p a nd a s s oc i a t ed ci rcu i try . 25. 1 s t a ndard pul se-w i d t h modula t i on mode th e c c p w i l l onl y fun c ti on in pwm m o d e . the pw m s i g nal i s us ed to s e t the op era t ing f r equ ency an d m a x i m u m al low a ble du ty cy cl e of t he mc p19 1 14/ 5 . fi gu re 25 -1 i s a s n ip pet of t he m c p19 1 14/5 bl oc k di a g r a m sh ow in g t h e p w m si g n a l f r om t h e c c p mo du l e . f i g ure 25- 1: mcp 191 1 4 /5 s n ip pe t s h owi n g sy ste m clock from p w m module th ere are tw o m ode s of ope rati on tha t c o n c ern th e sy st e m c l o c k p w m s i gn al . t h es e mo de s ar e s t an d-alone (no n -freque nc y s y n c h r oni za tio n ) an d frequ enc y sy n c hro n i z at ion . 25. 1.1 s t a nd-al o n e (non-freque ncy sy nchr o n i z ation) mode wh en the m c p191 1 4 /5 is ru nni ng st and - al one , th e pwm s i g nal fun c t i on s a s the sy st em cl oc k. it i s op era t in g at th e pro g ra mm ed s w itch i ng fre q u e nc y w i th a pro g ra mm ed m a xi mu m du ty cy c l e (d cl o ck ). th e pr ogra m m e d m a x i m u m du ty cy cl e is no t a d ju ste d on a cy cl e - by - c yc le ba si s t o co nt r o l t h e m c p 1 9 1 1 4 / 5 s y s t em ou tput . the requ ire d du ty c y c l e (d pd r vo n ) to c ont rol the o u tp ut is a d ju ste d by th e mc p1 91 14 /5 an al og c o n t rol l o o p an d as so ci ated ci rcu i try . d clo c k do es ho w e ve r s e t t he m a x i m u m al lo w a bl e d pd r vo n . eq ua t i o n 2 5 - 1 : 25. 1.2 s w i tchi ng freque ncy sy nchr o n i z ation m o d e th e mc p1 91 14 /5 ca n b e prog ram m e d to be s w itch in g fre que nc y m a s t er o r sl a ve de v i c e s . the m aster de vi ce fu nc tio n s as d e s c r i bed i n secti o n 2 5.1 .1 ? s t a nd-alon e (no n -freq u enc y sync hroniz a ti on) m ode? w i t h t h e ex ce p t i o n o f t h e s y s t em cl oc k al so be in g ap pl ied to gp a1. a s l a v e d e v i ce wi l l r e ce iv e t h e ma s t e r sy st e m cl o ck on g p a 1 . t h i s ma s t e r sy st e m c l oc k wi l l be o r ?e d w i th t he out put of the tim e r 2 mo dul e . thi s o r ?e d s i gn al w i ll latc h pw mr l int o pwm r h an d pwmphl i n to pwmphh. fi gur e 2 5 - 1 sh o w s a s i m p l i f i e d bl oc k d i ag r a m o f t h e c c p m od ule in pwm mo de . th e pwm p h l r egi ste r al low s for a ph as e s h if t to b e ad de d to the sla ve s y s t em c l oc k. it i s de si red t o ha ve th e m c p191 1 4 /5 sl a ve d e v i ce ? s sy st e m cl o ck s t a r t po i n t sh ift e d b y a p r o g r a mm ed am ou nt from the m aster sy ste m cl oc k. th is sla v e ph as e s h if t is s pec ifi ed by w r i t in g to the pwm p h l re gis t er . the sla ve pha se sh if t c a n be c a l c u l ate d b y us in g th e f oll ow in g e qua tio n. eq ua t i o n 2 5 - 2 : pwm s r q ov ove q 116 pwm signal from ccp d bu ck 1d cl o c k ? ? s l ave ph as e s h if t pwmph l t os c t2 pr escale value ?? ? ? = http:///
MCP19114/5 ds20005281a-page 144 ? 2014 microchip technology inc. figure 2 5 - 1 : si m p lifi e d p w m block di agra m a pwm out put ( f i gu re 2 5 -2 ) h a s a t i m e bas e (p erio d) a nd a ti me tha t th e o u tp ut s t a y s hi gh (dut y c y c l e ) . th e fre q u enc y of th e pw m i s the inv e rs e o f th e p e rio d ( 1/ p er i o d) . f i g ure 25- 2: pw m out p ut 25. 1.3 p w m pe rio d th e pw m p e ri od i s spe c i f ie d by w r i t ing to the pr 2 re gis t er . th e pw m peri od ca n be ca lcu l a t ed us ing th e fo llo w i ng eq uat ion . eq ua t i o n 2 5 - 3 : wh en tm r 2 is eq ual to pr 2 , th e fol l ow i ng tw o ev ent s oc c u r o n th e n e xt in crem en t c y c l e : ?t m r 2 i s c l e a r e d ? t h e pwm du ty c y c l e i s l a tc hed from pwm r l in to pwm r h en_ ss r sq q os c syst em clo ck la t ch da t a la t ch da t a r eset t i mer 8 8 8 8 com parator comparator com parator 8 8 8 8 pw mph l pw mr l w d m _ r eset pwmph h (sl ave ) pw mr h (sl ave ) tm r 2 ( not e 1) pr 2 c l kpi n _ i n note 1 : timer 2 should be clocked by f osc (8 mhz). pe riod du ty cy cl e t m r2 = pr2 + 1 tmr2 = pw mrh tmr2 = pr2 + 1 pwm perio d pr2 ?? 1 + ?? t os c t2 pr es ca le v a l u e ?? ? ? = http:///
? 2014 microchip technology inc. ds20005281a-page 145 mcp191 14/5 25. 1.4 p w m dut y c y cl e ( d cl o ck ) th e pwm du ty cy c l e (d cl o ck ) is s p e c if ied b y w r itin g to th e pw mrl reg i st er . up to 8-b i t res o lu tio n i s a v ai la ble . th e fo ll ow in g eq ua tion is us ed to ca lc ula t e th e pw m d u ty c y c l e (d cl o c k ). eq ua t i o n 2 5 - 4 : th e pwm r l b i t s c a n b e w r itte n to at any t i m e , but th e du ty c y c l e v a lu e is no t l a tc he d into pw mr h unt il af t e r a ma tch be tw een pr 2 a n d tm r 2 oc cu rs. 25. 2 o pera ti on dur i ng sleep wh en the dev ic e i s pla c e d in sle e p, the al loca te d ti me r w ill not inc r em en t and the st a t e o f the mo dul e w i l l no t ch ang e. if th e c l kpin pi n is driv in g a va lue , it w i l l c ont inu e to dri v e tha t va lue . wh en the dev ic e w a ke s up , i t wil l c ont inu e fro m thi s s t at e. pwm duty c y cl e pwmrl t osc t2 pr es cal e va lu e ?? ? ? = t able 2 5 -1: s um mar y of re giste r s ass o ciated wi t h pw m m o dule nam e bit 7 b it 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 regist e r on page m o de co n m s c 1 m s c 0 rfb ? ? ? ? ? 51 t2con ? ? ? ? ? t m r 2on t 2 c kps1 t2 ckps0 14 2 p r 2 t i m e r 2 m o d u l e pe r i od r e gi st e r 14 1 p w m r l p w m r e gi st e r lo w b y t e 14 3 * pw mph l phas e sh if t low byte 14 3 * le gen d : ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by pwm mode. * page provides register information. http:///
MCP19114/5 ds20005281a-page 146 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 147 mcp191 14/5 26 . 0 dual capture/comp are ( c c d ) module th e ccd m o d u l e i s i m p l e m e n t e d o n th e m c p1 9 1 1 4 / 5 . th is mo dul e is a n e w mo dul e ba se d on the st a nda rd c c p m od ule . it has tw o ca ptu r e a nd co mp are onl y re gis t er se t s w i th no pw m func ti on. 26.1 c apt ure mode in c apt ure mo de, t he c c x r h : c c x r l regi st er s et c apt ures the 16 -bi t v a l ue of th e tmr 1 re gis t e r w h e n a n ev ent o c c u rs o n th e d i mi p i n. an eve n t is de fine d a s o ne of th e f o ll ow in g: ? e v e ry fal l i ng edg e ? e v e ry risi n g e dge ?e v e r y 4 th ris i ng ed ge ?e v e r y 1 6 th r i si ng ed g e th e typ e o f e v e nt is co nfi gure d by co ntro l bit s ccxm 3 :ccx m0 ( c cdcon<3 : 0 > fo r re g i s t e r se t 1 o r ccdcon < 7 : 4 > fo r re g i ste r se t 2 ) . wh e n a c a p t u r e i s m ade , th e in terru pt re que st f l ag bit , c c x if (pir 1<2 > fo r re gis t er se t 1 or pir 1 <3 > f o r re gi ste r s e t 2), is se t. t h e in t e r r u p t f l ag m u st be c l ea r e d in so ftw ar e . i f an oth e r c apt ure o c c u rs bef ore t he v a l ue i n the reg i st er s e t i s read , th e o l d ca ptu r ed val u e is ov erw r i tten by th e ne w v a lu e. 26. 1.1 ccx pi n configura t i o n in c apt ure m o d e , t he d i m i p i n sho u l d be co nfi gure d as a n in pu t by s e tti ng the tris b i t fo r th at p i n . figure 26-1: cap ture mode o p er ation block dia g ra m 26. 1.2 t ime r 1 m o d e s e l e ct io n t i me r1 mu st b e run nin g of f of th e in stru cti on c l o c k for th e ccd m o d u l e to u s e th e c a p t u r e fe a t u r e . if t i m e r1 i s run n i ng o f f o f the 8 m h z cl oc k, t he c apt ure fe atu r e m a y no t fu nct i on co rrec t ly . 26. 1.3 s of twa r e inte rrupt w hen th e c apt ure m ode i s ch an ged , a f als e ca ptu r e i n ter r upt m a y be ge nera t ed . t he us er s h o u ld k eep th e e nab le for the ca ptu r e i n te rrupt cl ear in ord e r t o a v oi d fa ls e in terru pt s and s h o u ld cl ear th e fla g bi t, c c x if , fo ll ow in g an y s uc h c ha nge in the op erat ing m ode . 26. 1.4 ccd p r e s ca le r th ere are f our pre s c a le r s e t t ing s , s pec ifi e d by bit s ccxm 3 :ccx m0 . wh e n e v e r th e ccd re g i s t e r se t i s di sa bl ed or n o t s e t to c apt ure mo de, the pre s c a l e r co u n t e r is cl ea r e d. a n y r e se t wil l cl ea r t h e p r es ca le r c oun ter . sw it ch ing from on e ca ptu r e pre s c a l e r to ano the r ma y ge ne rate an in terru pt. als o , the pre s c a l e r c o u n te r wil l no t b e cle a re d, t here f ore , th e firs t c a p t ure ma y be from a n o n - ze ro pre s c a l e r . it is rec o m m en de d to d i s a bl e th e re gis t er set (c c x m 3 :0 = 00 xx ) pri o r to ch an gin g th e pr esc a l e r v a l ue. note : if the d i m i pi n i s c o n f igu r ed as an ou tput , a w r it e to the p ort c an ca use a c a pt ure c ond iti on. syst e m c l o ck (f os c ) ccdco n < ccx m 3 : 0 > ccxrh ccxrl tmr1h t m r 1 l capt ur e e nable ccd pin prescal e r 1, 4 , 16 s e t f lag bit ccx i f ( p i r 1 r e gis t e r ) and e dge det e c t http:///
MCP19114/5 ds20005281a-page 148 ? 2014 microchip technology inc. 26. 2 c omp a r e m ode i n c o m p a r e mo de , t h e 16 - b it c c d r x r e g i s t er v a lu e is c ons t a ntl y c o m p a r ed a g a i ns t th e tm r 1 regi ste r p a i r v a l ue. whe n a ma tch oc cu rs, the cm px pi n: ? i s d r i v en hi g h ?i s d r i v e n l o w ? t ogg le s ? r e m ai ns un ch ang ed th e a c ti on on the pi n i s based on the v a lu e o f th e co n t ro l b i t s , ccxm 3 :ccx m0 . at th e sa me t i me , i n terr upt fla g bi t, ccp1 i f , is se t. figure 26-2: comp ar e m o de op era t i o n blo c k diagra m 26. 2.1 c mp x pin config u r ation t h e us er mu st co n f ig ur e t h e c m p x p i n a s an ou t p ut by c l e a rin g th e tri s bi t for tha t pi n. 26. 2.2 t ime r 1 m o d e s e l e ct io n t i me r1 mu st b e run nin g of f of th e in stru cti on c l o c k for th e c c d mo du le to us e the co mp are fe atur e. if t i me r1 i s runn ing o f f of the 8 m h z cl oc k, the c o m p ar e fe atu r e m a y no t fu nct i on co rrec t ly . 26. 2.3 s of twa r e inte rrup t mode wh en ge ner ate sof t w a re in terru pt m o d e i s c h o s en , th e c c p 1 p i n is not a f fe ct ed. th e c c p 1if b i t is se t, c aus in g a c c x i n te rrupt (if ena ble d ). 2 6 . 2 . 4 s pec i a l e ven t t r i g g e r in th is m o d e , an in tern al ha rdware t r igg e r is g e ne rate d, w hi c h m ay be us ed to i ni t iat e a n a c ti on. the s pec ia l ev ent t r i g g e r out put o f c c d do es n o t res e t th e tm r 1 re gis t er p a i r an d s t a r t s an a/d co nv ers i on (if the a/d m odu le is en abl ed). special event trigger match tris output enable ccdcon mode select ccdrxh ccdrxl ccd pin set c cdxif interrupt flag (pir1) qs r output logic 4 tmr1h tmr1l comparator special event trigger will: - n ot set interrupt flag bit tmr1if in t he pir1 register. - set the g o/done bit t o start the adc conversion. note : c l eari ng th e c c x m < 3: 0> bi t s w i ll s e t the c m px co mp are ou tpu t la tc h t o t he def aul t s t at e. th is i s n o t th e g p io pin dat a la tch . th e de fau l t s t ate for s e t on ma tch or tog g le on ma t c h is 0 bu t the de fau l t s t a t e fo r c l ea r o n m a tc h i s 1 . note : th e s pec ia l ev ent t r igg e r fro m th e c c d m odu le w ill no t se t th e in terru pt f l ag bi t tm r 1if (bit 0 in the pir1 register). http:///
? 2014 microchip technology inc. ds20005281a-page 149 mcp191 14/5 26. 3 d ual capt ure/ comp ar e regi st er th e d ual c a ptu r e/c om p are m odu le is a n ew mo dul e b a se d o n th e s t an da rd c c p . it has no pwm fu nct i on . regist er 26-1: ccdcon: dua l captu r e /com p are control module r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 cc2m3 cc2m2 cc2m1 cc2m0 cc1 m3 c c 1 m 2 c c 1 m 1 cc1 m0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 4 c c 2m <3 : 0 >: cc reg i st er se t 2 mod e se le ct b i t s 00xx = c a p tu re/co m p a re of f (res e t s th e m o d u le ) 0100 = c apt ure m od e, e v e r y fall in g ed ge 0101 = capt ure m o d e , e v e r y ris i ng edg e 0110 = c apt ure m o d e , e v e r y 4 th r i s i ng ed g e 0111 = c apt ure m o d e , e v e r y 16 th r i si ng edg e 1000 = c om p a re m ode , s e t o u tpu t o n m a tc h (cc2if b i t i s s e t) 1001 = c om p a re m ode , c l ea r ou tput on ma tch (cc2if bi t is s e t) 1010 = c om p a re m ode , to ggl e ou tpu t on m a tc h (c c 2 i f bi t i s s e t) 1011 = r es erve d 11xx = c om p a re m ode , g ene rate s o f twa re inte rrup t o n m a tc h (cc2if bi t i s s e t , cm p2 p i n is una f f e c te d a nd co nfig ure d as a n i/o ) 1111 = c om p a r e m ode , t r igg e r sp ec ial eve n t (c c 2 if b i t is se t; c c 2 d o e s no t r e s e t tm r 1 ( 1 ) an d s t art s an a/d conv ersi on, if the a/d m odul e i s enab led . c m p2 pin i s una f fe ct ed and c onf igu r ed as an i/o po rt). bi t 3- 0 c c 1m <3 : 0 >: cc reg i st er se t 1 mod e se le ct b i t s 00xx = c apt ure/c o mp are of f (res e t s th e m o d u le ) 0100 = c apt ure m od e, e v e r y fall in g ed ge 0101 = c apt ure m o d e , e v e r y risi ng edg e 0110 = c apt ure m o d e , e v e r y 4 th r i s i ng ed g e 0111 = c apt ure m o d e , e v e r y 16 th r i si ng edg e 1000 = c om p a re m ode , s e t o u tpu t o n m a tc h (cc1if b i t i s s e t) 1001 = c om p a re m ode , c l ea r ou tput on ma tch (cc1if bi t is s e t) 1010 = c om p a re m ode , to ggl e ou tpu t on m a tc h (c c 1 i f bi t i s s e t) 1011 = r es erve d 11xx = c om p a re m ode , g ene rate s o f twa re inte rrup t o n m a tc h (cc1if bi t i s s e t , cm p1 p i n is una f f e c t ed a nd co nfig ure d as a n i/o ) 1111 = c o m p a re m ode , trig ger s pec ia l ev ent (c c 1 if bit i s s e t; c c 1 r e s e t s tm r 1 an d st ar t s an a / d c onv er sio n , i f the a / d mod u le is en able d . c m p1 pi n i s un af f e c t ed an d c o n f ig ured a s an i/o p o rt). note 1 : w hen the com p ar e in terru pt is se t, a pic wil l ty pi ca lly res e t tm r 1 . th is mo du le d o es no t re se t tm r1. http:///
MCP19114/5 ds20005281a-page 150 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 151 mcp191 14/5 27 .0 pw m control log i c th e pwm c o n t rol log ic i m p l e m en t s st a nda rd c o m p a r ator m odu les to ide n ti fy ev ent s su ch as in p u t u nde rvo l t a ge, in put o v erv o l t ag e and d e s a tur a tio n d e tec t i on. the c ont rol lo gic t a ke s ac tio n i n h a rd w a re to a ppro pria t el y en abl e/d i s abl e the ou tpu t d r iv e (pdr v / s d r v ), a s we ll as to s e t c o rres pon din g i n ter r upt fla g s to b e re ad by so f t w a re . th is co ntro l l ogi c a l s o de fin e s nor ma l pwm o pera t io n. f o r d e fin i ti on of i ndi vi dua l b i t s w i thi n t he co ntro l l ogi c, refe r to th e s p e c ia l f unc tio n r e gis t er (sfr ) s e c t io ns. f i g ure 27- 1: pw m con t r o l l o g i c sdrven pdrven ovlointp ovlointn ovloif uvlointp uvlointn uvloif uvloen ovlo ovloen delay delay sdrv pdrv ovintp ovintn ovif + - d en q ovout ov q1 oven pwmstr_sen pwmstr_pen + - desatp desatn mux default to desatp bg cdspol cdsintp cdsintn cdsif d en q cdsout q1 cdsoe cdswde wdm_reset s v s ov_ref d en q d en q q1 uvloout q1 ovloout cdsmux uvlo s + - e/aout ip druvif otif tmptby + - vdruvlo + - ot vdruvby s r q one shot sdrv_on one shot 200 ns 33 ns sdrv_on pwm pwm pwm http:///
MCP19114/5 ds20005281a-page 152 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 153 mcp191 14/5 28 .0 mas t e r sy nchr o nous se rial p o rt (ms sp ) module 28.1 m ssp modul e over view th e m a s t er sy n c hr ono us se rial po rt (m ssp) m odu le i s a s e ri al i n ter f ac e us efu l for c o m m u n ic ati ng w i th oth e r p e rip hera l or m i c r oc ont roll er d e v i c e s . th es e p e rip hera l d e v i c e s m a y be se rial eeprom s , s h if t re gis t ers , d i s p la y d r iv ers , a/d c onv erte rs , etc . th e m ssp m o dul e i n t he mc p1 91 14 /5 onl y op erat es in in ter-i ntegrated ci rc ui t (i 2 c) mo d e . th e i 2 c in terf ac e s upp ort s the fol l o w i n g mo des an d fe atu r es : ?m a s t e r m o d e ? s l a ve m ode ? b y t e n a c k i ng (slav e mo de) ? li m i t ed m ulti -ma st er s upp ort ? 7 - b it and 10 -bit add res s i n g ? s t a rt and s t op int e rrup t s ? i n t erru pt m a s k i n g ? c lo ck s t retc hi ng ? b u s c ol lis io n de tec t io n ? g en eral ca ll addres s m a t c h i ng ? d ua l ad dres s ma sk in g ? a d d re ss ho l d a n d da t a ho l d mo d e s ? s e l ec t a b l e sd a ho ld t i m e s fi gur e 2 8 - 1 is a blo c k dia g ram of th e i 2 c i n te rfa c e m odu le in m a s t er mo de. figu re 2 8 -2 is a di agr am of th e i 2 c in terf ac e m odu le in slav e m o d e . figure 28-1: ms sp block di ag r a m (i 2 c m a st er mod e ) read write sspsr s t ar t b it, stop bit, start bit detect, ssp buf internal data bus set/res e t : s, p , ssps t a t , wco l , ss px o v sh if t clo ck ms b lsb sda acknowledg e g e n e r a t e ( sspco n 2 ) s t o p b i t de tect w r ite c o llisio n d e t e c t c l o ck a r bi t r at i o n s t a t e c o un t e r fo r end of x m it /r c v scl scl in bus collision sda in receive en a b le ( rcen) clock c n tl c l o ck a r b i t r at e/b c ol de tect ( h ol d of f c l ock so ur ce) [ sspx m 3 : 0 ] b a ud rat e res e t sen, pen ( s s p co n2 ) generator (sspadd) addr es s ma t c h d e t e c t set sspif, bclif http:///
MCP19114/5 ds20005281a-page 154 ? 2014 microchip technology inc. figure 28-2: ms sp block di ag r a m (i 2 c sl a v e m o d e) 28. 2 i 2 c mode overview th e i n te r-inte g rat ed c i rc uit bus (i 2 c ) i s a m u lt i-m a s t er s e ri al d a t a co mm un ic atio n b u s. d e v i c e s com m unica te i n a m a s t er/ s l a v e en vi ronm en t, w h e r e th e m a s t er d e vi ce s ini t ia te the co mm un ic ati on. a sl av e d e v i ce i s c ont rolled thro ugh ad dres s i ng . th e i 2 c b u s sp ec ifi e s tw o s ig nal co nne cti o n s : ? s er i a l c l oc k ( s c l ) ? s e r i a l da t a (sda) bo th th e sc l a n d sd a con n e c ti ons are bid i re cti ona l o pen -drai n li nes , eac h req u i r ing p u ll -up re s i s t o r s fo r th e s upp ly vo lt a ge. pu lli ng t he l i ne to gro und is c o n s i dere d a lo gi cal z e ro; l e tti ng the l i ne fl oa t i s co nsi d e r ed a l ogi ca l o ne. fi gu re 2 8 -3 sh ow s a ty pic al c onn ec tion b etw e en tw o d e vi ce s con f ig ured as m a s t er a nd sl ave . th e i 2 c bus ca n op erat e w i th one or mo re m as t er d e vi ce s and one or mo re s l av e dev ic es . th ere are fo ur p o te nti a l mo des o f o perat io n f o r a g i ve n d e vi ce : ? m as ter t r ansmi t m o d e (m as ter is transm itt i ng dat a to a sla v e ) ? m as ter r e ce iv e m ode (m as ter is rec e iv in g d a t a from a sl ave ) ?s l a v e t r a n s m i t m o d e (s la ve is tran sm itt i ng da t a t o a ma ste r ) ? s la ve re ce iv e m o d e (s la ve is rec eiv in g d at a from a ma ste r ) t o b egi n c o m m u n ic ati o n , a m a s t er devic e s t art s o u t i n ma st e r t r a n s m i t mo de . t h e ma st e r de v i c e se nd s ou t a s t ar t b i t fo llo w ed by the a ddre s s by te of th e sl av e it i n ten d s to co mm un ic ate wi th. th is i s fo llo wed by a s i ng le r e ad/ w r i t e bi t, w h i c h d e te rmi nes w h et her th e m a s t er i n te nds to tra n s m i t to or re ce iv e d a t a from th e s l av e dev ic e. if th e re qu est ed sl av e e x i s t s on the b u s, it w i l l res p on d w i th an a c kn ow le dg e b i t, ot h er w i s e kn ow n as a n a c k . th e ma ste r th en c onti n u e s in e i the r t r ans mi t m o d e or r ec ei v e mo de a nd th e s l av e c ont inu es in th e c o m p le me nt, e i th er in r e ce iv e mo de o r t r ans m i t m ode , re sp ect i v ely . a s t a r t b i t is in dic a t ed by a hig h -to - low tran si tio n o f th e sd a lin e, w h i l e the sc l l i ne i s he ld hi gh. ad dres s an d da t a by tes are se nt o u t, mo st s i gn ifi c an t b i t (m sb) firs t. th e r e a d /w rite bit i s s ent o u t as a lo gic a l o n e w h en th e m a s t er in ten d s to read d a t a f r om t he s l av e, a nd is se nt ou t as a l o g i ca l z e ro w h en it i n ten d s to w r i t e d a t a to th e s l av e. f i g ure 28- 3: i 2 c m a ste r / slav e connec t io n th e ack now l edg e bit (ac k ) i s an ac tiv e -l ow sig n a l , w h i c h ho ld s t he sd a l i ne lo w to in dic a t e to th e tra n s m i tter tha t the s l av e dev ic e ha s rec e iv ed th e tra n s m i tted da t a a nd is read y to re ce iv e m o re. t h e t r an s i t i on o f a d a t a b i t is al w a ys pe r f o r m e d w h i l e th e sc l li ne is hel d lo w . t r ans iti ons tha t o c c u r w h i l e th e sc l li ne is hel d hig h are us ed to i ndi ca te s t art an d s t o p bi t s . if th e ma ste r i n te nds t o w r ite to th e sl ave , it repeatedly sends out a byte of data, with the slave responding after each byte with an ack bi t. in this ex am pl e, th e m a s t er d e v i ce is in ma ste r t r ans m it m o d e , an d th e s l av e is in slav e r e ce ive m ode . if the ma ste r in ten d s to re ad from the s l av e, it re pea ted l y re cei v e s a by te o f dat a from t he s lave and responds after each byte with an ack b i t. in this example, the master device is in master receive mode, and the slave is slave transmit mode. read write sspsr re g ma t c h d e tect s spadd reg s t ar t an d s t op bi t detect sspbuf reg internal da t a bu s a ddr ma tch s e t, re set s, p b i t s (sspstat reg) scl sda shift cloc k ms b lsb sspmsk1 reg ma st e r scl sda scl sda slave v dd v dd http:///
? 2014 microchip technology inc. ds20005281a-page 155 mcp191 14/5 o n th e las t by te of d at a c om m uni ca ted, t he m as t er device m a y en d th e t r ans m i ss io n b y sen d i ng a s t op bi t. if the m as t er dev ic e i s in r ec eiv e mo de, it se nds th e s t o p bi t i n p l ac e of t h e l a st a c k bi t. a s t op bi t i s i ndi ca ted by a l o w - to -hig h tran si tion o f the sd a lin e, w h ile the sc l l i ne is he ld hig h . i n s o m e ca se s, t h e m a s t er m a y wa nt t o ma i n ta in c ont rol of th e b u s and re-i ni tiat e an oth e r tr ans mi ss io n. if so, the m a s t er device may send another start bit in place of the stop bit or last ack bi t w he n it i s in r ec eiv e mo de . th e i 2 c b u s specifie s thre e m e s s a ge p r oto c o l s: ? s i ngl e m e s s a ge w h ere a m a s t er w r ite s d a t a to a sl a ve ? s i ngl e m e s s a ge w h ere a m a s t er reads d a t a fro m a s l a v e ? c om bi ne d m e s s a ge w h ere a m a s t er in i t iat e s a m i n i m u m of t w o w r it es, or t w o rea d s , or a c o m b in ati on of w r i t es an d re ads , to on e o r mo re s l av es when o ne de vi ce i s tran sm it ting a log i c a l on e, or le ttin g th e lin e flo at, an d a sec on d dev ic e is tr ans mi ttin g a l ogi ca l ze ro, o r h o ld in g the lin e lo w , the f i rst dev ic e ca n d etec t that th e l i ne is n ot a l ogi ca l o ne. th is de tec t io n, w h en use d o n t he sc l l i ne , is c a l l ed c l oc k stre tc hin g . c l ock str e tc hin g gi ves sl av e dev ic es a me ch ani sm to c ont rol th e flow of da t a . wh en th is de tect io n is u s ed o n th e sd a l i ne , i t i s ca lle d arbi trat ion . arb i tra t io n ens ure s th at th ere i s o nly on e ma st er de vic e c om m u ni c at ing at a n y si ngl e ti me . 28. 2.1 c lock s t re tching w hen a sl ave dev ic e ha s n o t co mp le ted p r oc es sin g d a t a , i t can d e l a y th e tran sfe r o f mo re dat a thro ugh th e p r oc ess of c l oc k s t re tch i n g . an add res s e d s l av e de v i c e ma y ho l d t h e sc l cl oc k li n e l o w aft e r r e ce iv i n g o r s e n d in g a b i t, in di cat i ng that i t is not y e t re ady to c ont inu e. th e ma st er tha t is c om m uni ca ting w i th th e s l a v e w i l l a tte mp t to ra is e t he sc l lin e in ord e r to tra n s f er th e nex t bi t, bu t wi ll d e te ct th at the clo c k lin e h a s no t y e t bee n re lea s e d . bec aus e the sc l c onn ec tio n is op en -drai n , t he s l a v e has th e ab ili ty to h old t hat li ne l ow unti l it is read y to c on t inu e c o m m u n ic at ing . c l ock s t retc hi ng all o w s rec e iv ers th at c a n not ke ep u p w i th a tran sm itt er to co ntro l t he f l ow o f in co mi ng dat a. 28. 2.2 a rbit ra t i o n ea ch m a s t er d e v i ce mu st m o n i tor t he bu s fo r s t art an d s t op bit s . if th e de vi ce det ect s t h at t he b us is bu sy , it c ann ot b e g i n a ne w me ss ag e u n til th e bu s retur n s to a n id le st a t e. h o w e ve r , tw o ma ste r de vic e s m a y tr y t o in itia te a tra ns m i s s i on at or abo ut the sa me tim e. wh en thi s oc c u rs , the p r oc es s of a r bi trati o n b egi ns . eac h tra n s m i tter ch ec ks th e l e v e l of the sda d a t a l i ne an d c o m p are s it to the lev e l tha t it exp e c t s to find. the firs t tra n s m i tter to ob se rve th at the two l e v e ls d o n' t ma tc h, l o se s a r bi trati on and mu st sto p tra n s m i ttin g o n th e sd a li n e . fo r ex am ple , if o n e tran sm itte r ho lds the sda lin e to a l ogi ca l on e ( l et s i t fl oat ) an d a se co nd tran sm itte r ho ld s i t to a log i c a l ze ro (p ul ls it low ) , th e re su lt i s tha t th e sd a l i ne w i l l b e l o w . t he f i rs t tra n s m i tter t hen ob se rve s th at the le ve l o f th e lin e i s dif f e r ent tha n exp ec t ed an d c onc lu des th at a not her transm itter is c o m m u n ic ati n g. th e fi rst t r ans m i tte r to n o tic e th is dif f e r enc e i s th e on e th at los e s a r bi trati on an d mu st sto p driv in g the sd a l i ne . if thi s tra n s m i tter i s al so a mas t e r d e v i c e , it m u s t al so s t o p dri v i ng th e sc l li ne . it the n ca n m o ni tor th e l i ne s for a s t op c ond iti on bef o re try i ng to rei s s u e it s tra n s m i s s i on . in the m e a n ti me , t he oth e r de vic e th at ha s not not ic ed any di f f e r en ce bet w een the ex pe cte d an d ac tua l le ve ls o n th e sd a lin e c onti nue s w i th it s or igi nal tran sm is si on. i t ca n do s o w i t h ou t an y c o m p li ca tio n s, b e c aus e so far the t r ans m i ss io n ap pe ars ex ac tly as e x p e c t ed, w i th no o t her tran sm itt e r di st urbi ng the me ss age . s l a v e t r an s m i t m od e c an al so be ar b i tr a t ed , w he n a m as t er add res s e s m ul t ip le sl av es, bu t th is is l es s co mm on . if tw o m a s t er de vi ce s are s end in g a me ss age t o tw o di f f eren t s l a v e dev ic es a t th e a ddr ess s t ag e, the m ast er se n d i n g th e l o w e r sl av e a d d r es s al w a ys w i ns ar bitr atio n. whe n t w o m a s t er de vic e s s e n d m e s s a g e s to the s a m e s l a v e add ress , and ad dre s s e s ca n s o m e ti me s re fer to m u lti p l e s l av es , th e arb i tra t io n pr oce s s m us t c onti nue in to t he dat a s t ag e. arb i tra t ion us ual ly oc c u rs v e ry rare ly , b u t i t is a ne ce ss ary pro c e s s for pro per m u l t i-m a s t er su ppo r t. http:///
MCP19114/5 ds20005281a-page 156 ? 2014 microchip technology inc. 28. 3 i 2 c mode operation al l m ssp i 2 c co mm un i c a t i o n is by t e - o r i e n t ed a n d s h i f ted ou t m s b fi rst. six sfr re gi ste r s a n d two inter r upt fla g s i n terf ac e t he mo dul e w i th the pic m i c r oc ont roll er a nd w i t h th e us er ? s so f t w a re . t w o p i ns , sd a an d sc l, are e x e r cis e d b y th e mo dul e to c o m m u n ic at e w i t h ot her ext e rna l i 2 c d e v i ce s. 28. 3.1 b y t e f o rm at al l co mm un ica t io n in i 2 c is d one i n 9-b i t se gm ent s. a by t e i s se nt f r o m a m a s t er t o a s l av e o r v ic e ve r s a , fo ll ow ed b y a n ack n o w led ge b i t s ent bac k. a f ter th e 8 th fa lli ng ed ge of th e sc l l i n e , the de vi ce ou tpu ttin g d a t a o n the sd a c han ges that p i n to a n inp u t an d re ads i n an ac kn ow l edg e v al ue on th e nex t cl oc k pu l s e . th e c l oc k s i g nal , sc l, is pro v i ded b y th e m a s t er . d a t a i s v ali d to ch ang e w hi l e the sc l si gna l i s lo w , an d sa mp l e d on t h e r i si n g e d g e of t h e c l o c k. c h an ge s on th e sd a li ne w h i l e the sc l lin e is hi gh de fine s p e c ia l c ond iti ons on th e bus , exp l a i ne d in th e foll ow in g se ct i o n s. 28. 3.2 d e f i n it io n o f i 2 c t e rm i n ol ogy th ere is lan gua ge an d term in olo g y i n the d e sc rip t io n of i 2 c c o m m uni ca tion tha t ha ve d e fi nit i on s s p e c if ic to i 2 c . su ch w o rd us ag e i s def ine d i n t a b l e 28-1 an d m a y b e us ed i n the re st of t h is doc um ent w i tho u t ex pl ana tio n. the i nfo rma t io n in thi s t a ble w a s ada pte d fro m the phil ip s i 2 c s pec if ic atio n. 28. 3.3 s d a a nd s c l p ins se lec t in g any i 2 c m ode wi th the sspen bi t s e t fo rc e s th e sc l and s d a p i ns t o be op en- drai n. the s e p i n s s hou ld b e se t by th e us er to i npu t s b y s e tti ng th e ap pro p ria t e t r is bi t s . 28. 3.4 s d a ho l d t i me th e ho ld tim e o f the sd a pi n is se le cte d by the sd ah t bi t in t h e sspcon3 regi s t er . hold ti m e i s the ti m e sda i s h e ld va lid af t e r th e fa lli ng edg e of sc l. se ttin g th e sd ah t bit se lec t s a lon ger 30 0 n s m i n i m u m ho ld time an d m a y he lp on bus es wi th la rge ca p a c i t a nc e. note : d a t a is ti e d t o o u t pu t z e ro w h en an i 2 c m ode is en ab led . ta b l e 2 8 - 1 : i 2 c bu s t e rms t e r m d e scr ip tion t r a n s m i tter t he dev ic e w h ic h s h if t s dat a ou t o n to the bus r e cei v e r the dev ic e w h ic h s hif t s dat a in fro m t he b us m as t er the dev ic e t hat ini t iates a tr ans fe r , ge ner ates c l oc k si gna ls an d te rmi nat es a tra ns f er sl av e t he dev ic e a ddr ess e d by th e m a s t er m u l t i-m a s t er a bu s w i th m o re tha n o ne d e v i c e th at c a n in iti a te dat a tra n s f ers arb i tra t io n p roc edu re to en su re th at o n l y o ne m a s t e r at a ti me co ntro ls the bus . w i nn ing arb i tra t io n ensure s t hat the me ss age is no t c o rru pted . sy nc hro n iz ati o n p roc edu re to s y nc hro n iz e the cl ock s of t w o or mo re d e v i ce s on t he bu s id le n o m a s t er i s c o n t rol lin g th e b u s an d bo th s d a and sc l l i n e s are hig h ac tiv e any tim e o ne or m o re ma ste r de vi ce s a r e c o n t rol lin g the b u s ad dres s ed sl av e s lav e d e v i c e th at h a s rec e i v ed a mat c h i ng ad dres s and is ac tiv e l y b e in g c l o c k ed by a m a s t er m a tc hi ng addre s s a ddre s s by te tha t is c l oc ke d i n to a s l a v e tha t ma tc hes th e v a lu e s t ore d i n ssp ad d x w r ite re q uest s lave re ce iv es a m a tc hi ng add ress wi th r / w bit clear and is ready to clock in data read request master sends an address byte with the r/w b i t se t , i n di ca t i n g t h at it w i sh es t o cl oc k da ta o u t of the slav e. thi s d a t a is the ne xt and al l fo llo w i ng by tes u n til a r e st art o r s t op. c l ock s t ret c hi ng whe n a dev ic e o n th e b u s hol ds sc l l o w to s t all c o m m u n ic ati o n bu s c o lli si on any tim e t he s d a lin e i s s a m p l ed low b y the module while it is outputting and expected high state http:///
? 2014 microchip technology inc. ds20005281a-page 157 mcp191 14/5 28. 3.5 s t a rt condition th e i 2 c spe c i f ic ati on def ine s a s t ar t c ond iti on as a tra n s i ti on o f sd a from a hi gh t o a l o w st ate, w h il e sc l l i ne i s hi gh. a s t art co ndi tio n is a l w a y s ge nera t ed b y th e m ast er an d si gni fie s th e tran si tio n of th e bu s fro m an idl e to a n ac tiv e st ate . fig u re 28-4 sho w s th e w a v e fo rms fo r s t art and s t op con d i t ion s . a b u s co lli si on c an oc cu r on a s t art c on dit ion if th e m o d u le s a m p l e s th e sd a l i ne l o w befo r e as se rtin g it l o w . th is doe s no t co nfo r m to the i 2 c s pe c if ic atio n th at s t at es no bus c o ll is ion ca n o c c u r o n a s t art. 28. 3.6 s t o p co ndit i o n a s t op c ond iti on is a tran sit i on o f the sd a li ne fro m low - to- h ig h s t ate w h i l e the sc l line is hi gh. 28. 3.7 r e s t a r t co ndit i o n a r es t art i s va lid a ny t i m e that a s t o p is v ali d. a m a s t er can is s ue a r e s t a r t if it w i s hes to ho ld the bu s af ter term in atin g t he cur r ent tran sfe r . a r e s t art has th e s a m e e f fe ct on the s l av e that a s t art w o uld , re se tting a ll s l av e l o g ic an d p r epa r in g i t t o c l oc k in an ad d r es s. th e m a s t er m a y w a n t to add r es s t he s a m e o r an oth e r s l av e. in 1 0 -b it add r es si ng sl av e mo de, a r e st art is req u ire d fo r t he ma st er to cl oc k dat a out of th e add r es se d s lav e. o n ce a sl av e h a s bee n f u ll y add res s e d , m atc hi ng bot h h i g h a nd lo w ad dres s by tes , the m ast er c an is su e a re s t art an d t he hig h a d dre s s b y te wi th th e r/w b i t s e t. t he s l a v e l o g i c w i ll then hold the clock and prepare to clock out data. after a full match with r/w c l e a r in 10-b i t mo de, a pri o r m a tc h fla g i s se t a nd ma int a in ed. u n t il a s top condition, a high address with r/w c l ea r or a hig h ad dre s s m a tc h fa ils . 28. 3.8 s t a rt / s t o p c o ndit i o n inte rrup t ma sk ing th e scie an d pcie bi t s i n the sspcon 3 regi s t er c a n en ab le th e gen erat ion o f an in terru pt in sl av e mo de s t ha t do n ot t y pi ca l l y su pp o r t th i s f u nc ti o n. t h es e b i t s w i l l h a v e no ef fec t o n s l av e m o d e s w here in terru pt o n s t art and s t op det ec t are al read y e nab le d. f i g ure 28- 4: i 2 c s t art an d s t op c o nd itions f i g ure 28- 5: i 2 c re s t art c o nd ition note : at le as t one sc l l o w tim e m u st a ppe ar b e for e a s t o p is v a l i d. th ere f ore , i f the sd a l i ne g oes low the n hig h ag ain w h ile th e sc l l i ne st ay s h i gh , o n ly th e s t art co ndi tio n i s de t e ct ed . sda scl p stop condition s st a r t c ond ition change of da t a al l o w e d c h ang e o f da t a al l o we d restart conditio n sr c han ge of da t a al l o we d change of data allow e d http:///
MCP19114/5 ds20005281a-page 158 ? 2014 microchip technology inc. 28. 3.9 a c k no w l ed ge s e q u e nce th e 9 th sc l p u ls e for a n y t r ans ferre d by te i n i 2 c i s d edi ca ted as a n ac k now l edg e. it a l l o w s rece i v in g d evi ce s t o re spo nd bac k to th e tra ns m i tter by pul lin g th e sd a li ne low . th e t r ans m i tte r m u s t re lea s e co ntro l o f the lin e du ring thi s ti me to s h if t in t he re spo n s e . th e ac kn ow le dge (ac k ) i s an a c ti ve - l ow si g n a l , pu l l i n g t h e sd a l i ne lo w , in di cat i ng to the tran sm itte r th at th e d e vi ce h a s r e ce iv ed th e tran sm itt ed da t a an d is r ead y to rec e i v e m o re. t h e result of an ack i s pl ac ed in th e ac kst a t bi t i n th e sspcon2 regi s t e r . sl av e so f t w a re , w hen t he ah en and d h en bi t s a r e s e t, al lows th e u s e r to s e t the ack v al ue se nt b ac k to th e tra n s m itter. the ac k d t bit in t h e sspcon2 re gis t er is se t/c lea r ed to d e te rmi ne the res pon se . s l a v e ha r d w a r e w i l l ge ne r a te a n a c k re sp ons e i f th e ahen and dhen bi t s in th e sspcon3 reg i s t er a r e cl ea r . th ere are c e rt ain conditions where an ack wi l l n o t b e s ent by th e s l a v e . if the bf b i t in t h e sspst a t reg i s t er o r the sspov bit in the sspco n 1 reg i s t er a r e s e t w h en a by te is rec eived, the ack w i l l no t b e se nt . w hen t he m odu le i s ad dres se d, af ter th e 8 th fal lin g e dge of scl o n th e b u s, the acktim b i t i n th e sspcon3 re gis t e r is s e t . the acktim bi t ind i c a te s th e ac kn ow le dge tim e of th e ac tiv e bu s. t he ac kti m s t at us b i t i s o n ly ac ti ve w h en t he ah en o r d h e n bit s a r e enab led . 28. 4 i 2 c slave m o de o perati o n th e m ssp sl av e m ode ope rate s i n o ne of th e fo ur m o d e s s e lec t ed in th e sspm b i t s in sspcon1 re gis t er . t he m ode s ca n be di vi ded i nto 7 - bit an d 1 0 -bi t add r ess i n g m ode . 10-b i t ad dres s i ng m o d e opera t e s t he sa me a s 7-b i t, w i th s om e add iti ona l o v er hea d for ha ndl ing th e la rge r ad dres se s. m o d e s w i th s t art a nd s t o p bi t int e rrup t s o pera t e th e s a m e a s th e o t her m o des , wit h sspif ad diti on all y g e tti ng se t u pon d e tec t i on of a s t a r t, r e st art, or s t o p c ond iti on. 2 8 . 4 . 1 s la ve mo d e ad d r ess es th e ssp a d d reg i s t er co nt a i ns the sl ave m o d e a ddre s s . th e fi rst by te re ce iv ed a f te r a s t a r t or r e st art c ond iti on is co mp ared ag ain s t the va lue st ored in thi s re gis t er . if t he b y t e m a tc hes , t he v a l ue is loa ded in to th e sspbuf reg i s t er an d an i n te rrupt i s ge ne rated . if th e v a l ue d oes no t m a tc h, t he m o d u le go es idl e a nd n o i ndi ca tio n is g i ve n to th e so f t w a re t hat a n y t hin g h app ene d. th e sspm sk1 reg i s ter af fe c t s the add res s m a tc hin g p r oc ess . r e fer to s ectio n 2 8 . 4. 10 ? sspm sk1 re gis t e r ? fo r m o re inf o rm atio n. 28. 4.2 s e c ond s l a v e mode a ddre ss th e ssp ad d 2 regi st er co nt a i ns a se co nd 7 - bit sl av e m ode ad dre s s . th e f i rst by te rec e iv ed af t e r a s t art or r e s t a r t co ndi tio n is c o m p a r ed a gai ns t the v a l ue s t ore d i n th is re gis t er . if th e b y te m a tc he s, the v a lu e is lo ade d i n to the sspbuf re gis ter and an int e rrup t i s ge ne rate d. if t he va lue d oes n ot ma tch , th e mo dul e go es idl e a nd n o in dic a t i on is giv e n to th e s o f t w a re th at an yt hin g h app ene d. th e sspm sk2 reg i s ter af fe c t s the a d d r es s m a tc hin g pr oce s s . r e fer to se ctio n 2 8 . 4.1 0 ? sspm sk1 re g i s t e r ? fo r m o re info rm a t io n. 28. 4.2. 1 i 2 c s l a v e 7- bi t a ddr es s i ng mod e in 7-b i t addre s s i n g m o d e , t he lsb of t he rec e iv ed dat a by te i s i gno red w h en de term in ing if th ere i s an a d d r es s ma t c h . 28. 4.2. 2 i 2 c s l a v e 10- bi t a ddr e s s i n g mo de in 10-b i t ad dre s s i ng mo de, the f i rs t rec e iv ed by te i s co mpa r ed t o t h e b i na r y v a l u e o f ? 1 1 1 1 0 a9 a8 0 ?. a 9 an d a 8 ar e t he t w o m s b o f t h e 1 0 - bi t ad dr e s s an d a r e s t ore d i n b i t s 2 and 1 i n th e ssp ad d reg i s t er . a fte r t h e h i gh b y t e h a s be e n ac kn ow l e dg e d , t h e u a bi t i s se t a nd sc l is hel d low un til th e us er upd ate s ssp ad d w i th the lo w a ddre s s . t he lo w ad dre s s b y te i s c l oc k ed in and a l l 8 bit s are c o m p a r ed t o the l o w ad dre s s val u e i n ssp ad d . even if th ere i s no a d d r es s m a tc h, s spif a nd u a are se t, an d sc l is he ld low u n ti l s s p a d d i s up da t e d t o r e c e i v e a h i g h by te a g a i n. w h en ssp ad d i s up dat ed, th e u a b i t is c l e a red . thi s en su res the m od ule is re ad y to re ce iv e the hig h ad dre s s by te on t he n e x t c o m m u n ic ati on. a h i gh an d l o w ad dre s s ma tc h as a w r ite req ues t i s re qui red at t he st a r t o f al l 1 0 -b it a d dr essi n g c om m u nic ati on . a tran sm is si on c an be i nit iate d b y i s s uin g a r es t art onc e the sl av e i s a ddre s s ed , an d c l oc k i ng in the hi gh add ress w i th the r / w b i t se t. th e s l av e h a rdw a re w i l l th en a c k n ow l edg e th e rea d re que st a nd prep are t o c l oc k o u t d a t a . th is i s o n l y v a li d for a sla v e a f ter it ha s rec e iv ed a c o m p le te hig h an d l o w a ddre ss-byte match. 28.4.3 slave reception when the r/w bi t o f a ma tc hin g re ce iv ed add res s by te is c l ea r , t he r/w b i t in the sspst a t re gis te r is c l e a re d. th e rec e iv ed a ddre s s i s lo ade d i n to th e sspbuf re gis t er and ac kn ow le dge d. wh en an ov erf l ow co ndi tio n e x i s t s f o r a re cei v e d ad dre s s , th en n o t ac kn ow le dge is gi ve n. an ov erfl ow c ond iti on is de fin ed as ei the r bi t bf in th e sspst a t re gis t er is s e t, o r b i t sspov i n the sspcon1 reg i s t er i s s e t. the boen bit i n the sspcon3 reg i s t er m o di fie s th is op erat ion . f o r m o re in form at ion, re fer to r e gi st e r 28 - 4 . http:///
? 2014 microchip technology inc. ds20005281a-page 159 mcp191 14/5 an m ssp in terru pt is ge nera ted f o r ea c h tr ans ferre d d a t a b y te . fla g bi t, sspif , m u s t b e c l ea red b y s o f t wa re. w hen the sen b i t in the sspcon2 re gi s t e r is s e t, scl w ill b e he ld lo w ( c lo ck st re tch ) f o ll ow in g ea ch r e cei v ed byt e . th e cl ock must be re lea s ed by s e t t in g t h e c k p bi t in th e sspcon1 reg i s t er , ex c e pt s o m e tim e s i n 1 0 -bi t m ode . 28. 4.3.1 7 - b i t a ddres si ng rec ept ion th is se cti on d e sc rib e s a st and ard s e q uen ce o f ev ent s fo r th e m ssp m o d u l e c o n figu r ed as a n i 2 c sl av e i n 7 - bit add r es si ng mo de, in cl uding all d e c i si on s m a d e b y hard w are or s o f t w a re and th eir ef fec t on rec e p t io n. fi gu res 28-5 an d 28-6 a r e us ed as a v i s u a l refer ence fo r th is descr ipti on. th is is a s t ep -by - ste p p r oc es s o f w hat typ i c a ll y m u s t b e do ne to a c c o m p l i s h i 2 c c om m u nic ati on. 1 . s t art bi t de tec t ed . 2 . s b i t i n t he ssp st a t re gis t e r is s e t; sspi f is s e t i f in terru pt o n s t a r t de tec t is e nab led . 3 . m a tc hi ng a ddre s s w i th r / w bi t cl ear i s rec e i v e d . 4 . th e sl ave p u lls sda low sending an ack to th e m a s t er , an d s e t s sspif bit . 5 . so f tware cl ea rs th e ssp if bi t. 6 . so f t ware rea d s rec e iv ed add res s f r om sspbuf c l ea rin g th e bf fla g . 7 . if sen = 1 , s l av e s o ft w a r e se ts c k p bi t t o r e l e as e t h e s c l li n e . 8 . th e m as t er cl ock s out a d at a by te. 9 . sl av e dri v e s sd a l o w s end ing an ac k to th e m a s t er , an d s e t s sspif bit . 1 0 . s o f tware c l ea rs sspi f . 1 1 . s o f tware read s th e rec e iv ed by t e from sspbuf cl e a r i ng b f . 1 2 . s tep s 8?1 2 are repe ate d f o r a ll rec e i v ed b y te s f r om t h e m a s t er . 1 3 . m as ter se nd s s t op co ndi tio n , se ttin g p b i t in th e sspst a t re gis t er , an d th e b u s goe s i d l e . 28. 4.3. 2 7 - b i t rec e p t io n wi th a h e n an d dhe n sl ave dev ic e rec ept ion w i th ah en and d h e n s e t op era t es th e s a m e as w i t hou t th es e o p ti ons w i th ext r a i n terr upt s an d cl oc k s t retc hi ng a dde d af t e r the 8 th fa lli ng e dge o f sc l . the s e ad di tional i n terr upt s all o w th e sl av e so f t w a r e to de ci de w h ethe r it w a n t s t h e a ck to re ce iv e add res s or da t a by te, ra the r th an th e ha rdwa re. th is li st de sc rib e s the s t ep s that ne ed to be t a k e n b y s l av e s o f t w a r e to use the s e o p ti ons for i 2 c co mm un i c a t io n. figu re 2 8 -7 d i s p la ys a mo du le us in g bo th a ddre s s an d da t a ho ld ing . fig u re 28-8 i nc l ud es th e op erat ion w i th th e sen bi t in t h e sspcon2 re gis t er se t. 1. s b i t i n th e sspst a t re gis t er is s e t; sspi f is s e t i f in terru pt o n s t art de tec t is en ab led . 2. m a tc hi ng ad dre s s w i th r / w b i t cl ear i s c l oc ke d i n . sspif is s e t and ckp c l eare d af te r th e 8 th fa lli ng edg e o f sc l. 3. sl ave c l ea rs t he s spif . 4 . s l a v e ca n lo ok at t h e a c k t i m bi t in t h e sspcon3 regi s t e r to de term in e i f th e sspif was after or before the ack . 5. sl av e re ads the ad dres s v a lu e from sspbuf, clearing the bf flag. 6. slave sets ack va lue c loc ke d o u t to the m a st er by s e tti ng ackdt . 7. sl ave rel eas es th e c l oc k by se ttin g c k p . 8. sspx if i s s e t af t e r an ack , n o t a f te r a nack. 9. if sen = 1 t h e s l av e h a r dw a r e will stretch the clock after the ack . 10 . s l a ve c l ea rs ssp if . 1 1 . sspif s e t an d ckp c l ea red af ter 8 th fal lin g edg e of sc l f o r a rec e iv ed da t a b y te . 12 . s l a v e loo k s a t acktim b i t in t he sspcon3 re gis t er to d e te rmi ne t he s o u r ce of the int e rrup t . 13 . s l a v e re ads t he rec e i v ed d a t a fro m sspbuf cl e a r i ng b f . 14 . s tep s 7?1 4 are the s a m e f o r e a c h re ce iv ed dat a by te . 15 . c om m uni ca tio n is e nde d by eit her the slave sending an ack = 1 or the m ast er sen d i ng a s t op co ndi tio n . i f a s t o p i s s e n t an d in terru pt o n s t op d e te ct i s d i s abl ed, the sl av e w i l l o n ly kn ow by p o ll ing the p b i t i n th e sspst a t re gis t er . note : sspif is s ti l l s e t af t e r th e 9 th fall in g ed ge of sc l ev en if t here is no c l oc k s t retc hi ng an d bf h a s bee n cl ea red. o n ly i f n a c k is se nt to m a s t er is sspi f no t s e t. http:///
MCP19114/5 ds20005281a-page 160 ? 2014 microchip technology inc. f i g ure 28- 6: i 2 c s l ave , 7 - bi t addre ss , re ce ption (s en = 0 , a h en = 0 , dhe n = 0 ) r e c e i v in g a d dr e s s ack r e ce iv in g d a ta ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspi f bf sspov 1 2 3 4 56 78 1 2 3 456 7 8 12345678 cleared by software sspbuf is read cleared by software p s from slave to master sspif set on 9 th falling edge of scl f i rs t by te of da ta i s av ai l ab l e i n sspb u f b u s m a s t er se n d s s t op co nd i t i o n sspov s e t be c a us e sspbuf i s s til l f u ll . ack is no t s e nt. 9 9 9 http:///
? 2014 microchip technology inc. ds20005281a-page 161 MCP19114/5 f i g ure 28- 7: i 2 c s l ave , 7 - bi t addre ss , re ce ption (s en = 1 , a h en = 0 , dhe n = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p ack ckp sspo v bf sspif cleared by software cleared by software sspbuf is read s ack ack r e c e iv e addre s s r ec ei ve d a t a r e ce iv e d a t a r/w = 0 b u s ma ste r se nds s t o p c ond iti o n sspif s e t on 9 th fal lin g ed ge of sc l c l o c k is h e ld lo w un til c kp is se t to ? 1 ? fi rst by te of da t a i s av ai lab l e i n sspbuf sspov s e t b e c a us e sspbuf is s t i l l ful l . ack is not sent. ckp i s wri tte n to ? 1 ? i n s o ft w a r e , re lea s i ng sc l ckp is writte n t o ? 1 ? in s o f t w a re, r e le as ing sc l sc l is no t he ld lo w be ca u s e ack = 1 http:///
MCP19114/5 ds20005281a-page 162 ? 2014 microchip technology inc. f i g ure 28- 8: i 2 c s l ave , 7 - bi t addre ss , re ce ption (s en = 0 , a h en = 1 , dhe n = 1 ) r e c ei v i n g a d dr e s s r ec ei vi n g d a ta r ec e iv ed d ata p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 sda sc l bf ckp s p 12 3 4 5 6 7 8 9 12 3 45 6 78 9 1 2 3 4 5 678 s da t a is re ad from sspbuf cleared by sof t w a re 9 ack = 1 ack ackdt acktim sspif ack if ahen = 1 , sspif is s e t sspif is s e t on 9 th f all in g ed ge of sc l, af te r ac k address is r e ad f r om ssbuf sla v e s o f t ware c l ears ackdt to ack t h e r e ce iv ed by t e wh en ahen = 1 : c k p is cleared by hardware and scl is stretched ac kti m s e t by har dw are on 8 th fal lin g e dge of sc l no i n terr upt af ter not ack from slave slave soft w a re s e t s ackdt t o no t a c k when dhen = 1 : c kp is cl ea red b y hard w are on 8 th fa lli ng edg e o f sc l ckp s e t b y s o f t ware , sc l i s rele as ed ac ktim cl ear ed b y hard w are on 9 th ris i ng ed ge o f sc l ac kti m s e t by hard w are on 8 th fal lin g ed ge of sc l ma st e r re l e as es s d a x to sl av e fo r ack s equ en ce master sends st o p c o n d i t i o n d7 d6 d5 d4 d3 d2 d1 d0 http:///
? 2014 microchip technology inc. ds20005281a-page 163 MCP19114/5 f i g ure 28- 9: i 2 c s l ave , 7 - bi t addre ss , re ce ption (s en = 1 , a h en = 1 , dhe n = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ackdt ckp s p s 12 34 567 8 9 12 3 45 67 8 9 12 34 5678 9 cleared by software slave software clears ackdt to ack the received byte p master sends stop condition acktim r/w = 0 ack ma ste r rel eas es sda to slave for ack sequence ack re ce i v e d ad dre s s is lo ade d i n to sspbuf r e ce iv ed da ta i s a v ai la ble o n sspbuf sspbuf c a n be read an y t i m e be fore nex t b y te is lo ade d no interrupt after if not ack from slave s l av e s en d s no t ac k whe n ahen = 1 : on the 8 th f a ll i ng ed ge of sc l of an a ddr ess byt e , c kp is cl eare d wh e n dhen = 1 : on the 8 th fal lin g e dge of sc l o f a rec e i v ed dat a by te, c kp is cle a r e d set by s o f t ware , rel e a s e scl c kp i s not cl eare d i f no t ack acktim i s s e t b y hard w are on 8 th f a ll ing ed ge of sc l ac ktim is c l ea red by ha rdw a re on 9 th ri si ng edg e o f sc l http:///
MCP19114/5 ds20005281a-page 164 ? 2014 microchip technology inc. 2 8 . 4 . 4 s la ve t r an sm i s s i on w hen the r / w b i t o f t h e i n co mi ng ad d r es s by t e i s se t and an address match occurs, the r/w bi t in th e sspst a t re gis t e r is s e t. the rec e i v e d a ddre s s i s loaded into the sspbuf register and an ack pu ls e i s s ent by the s l av e o n th e 9 th bi t. following the ack , s l av e har dw are cl ea rs the c kp b i t a nd the sc l p i n is hel d low . r e f e r to sect ion 2 8.4 . 7 ? c lock s t retc hing? for m o re d e t a ils . by s t ret c hi ng th e c l o c k , the m a s t er w i ll b e una ble to as s e rt an oth e r cl oc k p uls e un til th e sl av e is d one prep arin g the t r ans m i t da ta. th e tra n s m i t dat a m u s t b e lo ade d in to th e sspbuf re gis ter , whi c h als o loa d s the sspsr reg i s ter . the n th e sc l pin s hou ld be r e le as ed b y set t in g th e c kp b i t i n th e sspcon1 re gis ter . the eig h t d a t a bit s are s h if te d o u t on th e fal lin g ed ge of th e sc l in put. t h is ens ure s th at t he sd a si gna l i s v a l i d duri ng the sc l h i gh tim e . the a c k pulse f r om the master- r eceiver is latched on the r i sing edge of the 9 th scl input pulse. this ack value is copied to the ackstat bit in the sspcon2 register. if ackstat is set (not ack ) , the dat a t r ansfer is com p lete. i n this case, when the not ack is lat c hed by the slave, t he slave goes idle and w a its for another occurre nce of th e s tart bit. if the sda line was low (ack ) , the next transmit dat a must be loa ded in to t he ss pbu f register . a gain, the sc l pin must b e re leased by setti ng bit c k p . an m ssp in terru pt i s gen era ted for eac h d a t a tra n s fer b y te . the ssp if bit m u s t be c l e a red by s o f t w are an d th e sspst a t regi s t e r is u s e d to d e te rm i ne th e s t atu s o f t he by te. th e sspif bi t i s s e t on th e fall in g edg e of th e 9 th cl oc k p u l s e. 28. 4.4.1 s l a v e m ode bu s c o ll is io n a sl av e re ce iv es a r ea d re que st an d beg ins s hi f tin g d a t a ou t on th e sd a lin e. i f a bus c o l lis io n i s d e te cte d a nd the sbcde bit in th e sspco n 3 re gis t e r is s e t , th e b c li f b i t in t h e p i r r e g is t er i s se t. onc e a bu s co ll is i o n is de t e c t ed , t h e sl av e g o e s id le a n d w a its t o be a ddres s e d a gai n. th e us er ? s s o f t w a re c an u s e th e bc l i f b i t to ha ndl e a sl av e b u s co lli si on. 28. 4.4. 2 7 - b i t t r ans mi ss io n a m a s t er de vice ca n tra n s m i t a read req u e s t t o a sl av e an d the n it c l oc ks dat a out o f t he sl av e. th e lis t bel ow ou tli nes w h a t s o f t w a re fo r a s l a v e w i ll nee d to do to ac c o m p li sh a s t an dard t r ans mi ss io n. f i gu r e 2 8 - 10 ca n be us ed as a r e ferenc e to th is lis t. 1. m a s t er se nd s a s t art c ond iti on on sd a an d scl. 2. s b i t i n th e ssps t a t re gis ter is s e t; sspi f is s e t i f in terru pt o n s t art de tec t is en ab led . 3. m a tc hi ng ad dres s w i t h r / w b i t se t i s r e ce i v e d by th e sl av e s e tti ng sspif b i t. 4. sl ave h a rdw are generates an ack an d s et s sspif . 5. sspif bi t is c l ea red by us er . 6. so f t w a re read s t he re ce iv ed a ddre s s from sspbuf , c l ea rin g bf . 7. r / w i s se t s o c k p w a s au tomatically cleared after the ack . 8. th e s l av e s o f t w a re loa d s the tran sm it d a t a in to sspbuf . 9 . c k p bi t i s se t r e le as i n g s c l, a l lo w i ng t h e m a s t er t o c l oc k the dat a o u t o f th e slave. 10. sspif is set after the ack r e sp on se fr o m t h e m a s t er i s loa ded in to th e ac kst a t re gis t er . 1 1 . sspif bi t is c l ea red. 12 . t h e sl av e s o f t w a re ch ec ks the ac kst a t bi t to s ee if th e m as t er w ant s to c l oc k out mo re d at a. 13 . s tep s 9 ?13 are repe ate d fo r ea ch trans m itte d by te . 14 . if the m a st er s e n d s a n o t ack , th e c l o c k is n o t he ld , bu t sspif is s t ill s e t. 15 . t h e ma ste r s end s a r e s t art co ndi tio n or a s t o p . 16 . t h e s l a v e is no lon ger add res s e d . note 1 : if the master ack s, the clock will b e s t retc he d. 2: ac kst a t i s the on ly bi t u pda ted on th e ri sin g e dge of sc l (9 th ) rath er th an o n th e fa lli ng edg e. http:///
? 2014 microchip technology inc. ds20005281a-page 165 MCP19114/5 f i g ure 28- 10 : i 2 c s l ave , 7 - bi t addre ss , t ransm i s s ion (ahe n = 0 ) r e ce i v i n g a d d r e s s automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspi f bf ckp ackst a t r/ w d/a s p set by software cleared by software s p r/w = 1 ack ack ack ma ste r se nds s t op co nd i t io n r e ce iv ed ad d r es s i s re ad from sspbuf when r/w is s e t, scl is al way s h e ld lo w af t e r 9 th scl f a ll ing ed ge da t a to tra n s m i t is l o a ded into sspbuf bf is auto ma tic a l l y cl ea r e d a f t e r 8 th f a ll ing ed ge of sc l ckp is not held for not ack master?s not ack is co pie d t o ackst a t r/w i s c o p i ed from th e ma tch i ng ad dres s by te indicates an address has been received http:///
MCP19114/5 ds20005281a-page 166 ? 2014 microchip technology inc. 2 8 . 4 . 4 . 3 7 - b it t r an sm is si on w i t h ad dr es s hol d e nab led se ttin g th e ahen bi t in the sspcon 3 reg i s t er en a b l e s ad di t i on al cl oc k st r e t c hi n g an d i n t e r r u p t g ene rati on a f ter t he 8 th fal lin g ed ge o f a re ce ive d m atc hi ng ad dres s. o nc e a m atc hi ng ad dres s ha s b een c l o c k e d i n , ckp is c l eare d an d the sspif i nter r upt is se t. fi gu re 2 8 -1 1 di sp lay s a st a nda rd w av efo rm o f a 7-b i t ad dres s slav e t r ans mi ss io n w i th ah en e nab led . 1. b us sta r ts i dle . 2 . m a s t er se nds s t a r t c ond iti on; th e s bi t in th e sspst a t reg i s t er is s e t ; sspif is s e t if in terru pt o n s t art det ec t is en abl ed . 3 . m a s t er s end s ma tch i n g add res s w i th r / w bi t s e t. af te r th e 8 th f a ll ing e dge of th e sc l l i ne , th e ckp bi t is c l eare d an d sspif in terr upt i s g ene rate d. 4 . sl av e s o f t wa re c l e a rs sspif . 5 . sl av e s o f t w a re reads acktim bit in the sspcon3 register and r/w a nd d / a b i t s in th e sspst a t re gis te r to det erm i ne the s ourc e of th e i n te rrupt . 6 . sl av e rea d s th e ad dres s v a l ue fro m th e sspbuf reg i s t er c l ea rin g th e bf bit . 7 . sl av e s o f t w a re de ci des from th is i n fo rma t io n i f it wi s h e s to ack or not ack and s e t s ac k d t b i t i n th e sspcon2 re gi s t e r ac c o rdi ngl y . 8 . sl av e s e t s the c kp b i t re lea s i ng sc l. 9 . m a s t er clo c k s in the ac k v a l u e f r om th e sl av e. 1 0 . s l a v e ha rdw a re automatically clears the ckp bit and sets sspif after the ack if the r/w bi t is se t . 1 1 . s l a v e s o f t wa re c l e a rs sspif . 1 2. s l av e lo ads va lue to trans m i t to th e ma st er in to sspbuf s e ttin g th e bf bi t. 1 3 . s l a v e s e t s c kp bi t re lea s i ng the cl ock . 1 4 . m as ter c l o c k s o u t t he d a t a from the sl av e an d s end s an a c k v a l u e o n t h e 9 th sc l pu ls e. 1 5 . s l a v e har dw are c o pies the ack v a l ue i n to th e ackst a t bi t i n th e sspcon2 re gi s t e r . 1 6 . s tep s 1 0?1 5 are repe ate d for e a ch by te t r an sm it t e d t o t h e m a s t er f r om th e sl av e. 1 7 . i f t he m a s t er s end s a not ack , th e s l av e re lea s e s the bus a l l o w i ng the master to send a stop and end the communication. note: sspbuf cannot be loaded un ti l af ter th e ack . note: master must send a not ack on th e las t b y te to e n su re th at th e s l av e re lea s es the scl line to receive a stop. http:///
? 2014 microchip technology inc. ds20005281a-page 167 MCP19114/5 figure 28-1 1 : i 2 c s l ave , 7 - bi t addre ss , t ransm i s s ion (ahe n = 1 ) r e c e iv in g ad dres s automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ackdt ackst a t ckp r/w d/a cleared by software s p ack ack ack acktim r/w = 1 r e c e i v e d ad dre s s is re ad from sspbuf slave clears ackdt to ack ad dre s s dat a to tra n sm it is l oad ed into sspbuf b f is au tom ati ca lly c l e a re d af ter 8 th f a ll ing ed ge of sc l ma st er ? s a c k res po nse is c opi ed to sspst a t c kp not cleared aft e r n o t a c k wh en ahen = 1 : ckp i s c l e a red by ha rdwa re af ter r e ce iv ing m a tc hin g ad dre s s . when r/w = 1 : ckp is always cleared after ack se t by s o f t wa re, r el e as es s c l ackt im i s s e t on 8 th fa ll ing e dge of scl acktim is s e t o n 9 th ris i ng edg e o f sc l ma st e r se nd s s t op co ndi tio n http:///
MCP19114/5 ds20005281a-page 168 ? 2014 microchip technology inc. 28. 4.5 s l a v e m o de 1 0 - b i t addr es s rec e p t ion th is se cti on d e sc rib e s a st and ard s e q uen ce o f ev ent s fo r th e m ssp m o d u l e c o n figu r ed as a n i 2 c sl av e i n 1 0-bi t add r es si ng mo de. fi gu re 2 8 -12 is us ed as a v i s u a l re feren c e for thi s de s c r i pt i on . th is i s a st ep-by -s tep p r oc es s of w hat m us t b e don e by sl av e s o ft w a r e t o a c co mp li sh i 2 c co mm un i c a t io n. 1. b us sta r ts i dle . 2 . m a s ter s e n d s s t art c o ndi tio n ; s bit in the ssp- st a t re gis ter is s e t; sspif i s s e t if in terru pt o n s t ar t de tect is en ab led . 3 . m as t er s en ds ma tch i ng hi gh a ddre s s w i th r / w b i t c l e a r; ua bit in t he sspst a t register is set. 4. slave sends ack and sspif is s e t. 5 . so f t w a re cl ea rs t he ssp if bi t. 6 . so f t ware rea d s rec e iv ed add res s f r om sspbuf c l e a rin g th e bf fla g . 7 . sl av e loa d s low ad dres s i n to ss p a d d , re lea s i ng sc l. 8 . m a s t er sen d s m a tching low-address byte to the slave; ua bit is set. 9. slave sends ack and sspif is s e t. 1 0 . s l a v e c l ea rs sspif . 1 1 . s l a v e re ads t he rec e iv ed m a tc hin g add res s fro m sspbuf c l ea rin g bf . 1 2 . s l a v e lo ad s h i gh ad dres s int o ssp ad d . 1 3 . m as ter c l o c k s a dat a by te t o th e sl av e an d cl oc ks ou t t h e sl a v e ?s ack on th e 9 th sc l pu ls e; sspi f is s e t. 1 4 . i f sen bi t i n the sspcon2 reg i s t er is s e t, ckp i s cl eare d by ha rdw a re a nd the c l o c k i s s t ret c he d. 1 5 . s l a v e c l ea rs sspif . 1 6 . s l a v e rea d s t he re c e iv ed b y te from sspbuf cl ea r i ng b f . 1 7 . i f sen is set, t he s l av e se t s c kp to re lea s e th e scl . 1 8 . s tep s 13?1 7 are re pea ted fo r ea ch re ce ive d by t e. 1 9. m as ter sen ds s t op to e nd the tran sm is si on. 28. 4.6 10-b i t a ddre ss ing wi th ad dres s o r dat a hold r e ce pt i o n us i n g 10 - b i t ad d r e s si ng w i t h ah e n o r d h e n se t i s t h e sa me as w i t h 7 - bi t mo de s. t h e on ly di f f e ren c e is the n eed to u pda te t he ssp ad d reg i st er us in g t he u a bi t. al l fu nc tio nal ity , sp ec ific al ly w h e n th e c kp bi t is cl eared an d sc l li ne i s h e ld low , i s th e sa me . fig u re 28 -13 c an be u s e d as a re fere nce of a s l av e in 1 0 -b it a ddre s s i n g w i t h ah en s e t. fi gur e 2 8 - 14 sho w s a st and ar d w a ve for m for a sl av e tra n s m i tter in 1 0 -b it ad dre s s i ng mo de . note : u p d a te s to t he ssp ad d regi ste r are n o t al l o w e d un t i l aft e r t h e a c k se qu enc e. note : if th e low ad dres s do es n o t m a tc h , sspif a nd u a are sti l l s e t s o th at th e s l av e so ftw ar e ca n s e t s s p a d d b a c k t o t h e h i gh a ddre s s . bf is n o t se t be ca us e t here is n o m a tc h. c kp is un af fec t ed. http:///
? 2014 microchip technology inc. ds20005281a-page 169 MCP19114/5 f i g ure 28- 12 : i 2 c s l ave , 1 0 -bit addr es s, rece ption ( s en = 1 , ahe n = 0 , dhe n = 0 ) sspif receive first address byte ack receive second address byte ack re c e i v e da t a ack re c e i v e da t a ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1234567 8 9 1 2345678 9 12345678 9 12345678 9 p cleared by software s bf m a s t er se nds st o p c o n d i t i o n se t by ha r d w a r e on 9 th fal l i ng edg e if ad dre s s ma tc hes ssp add, it i s loa d e d i n to sspbuf wh en u a = 1 : sc l is hel d low sof t ware upd ate s ssp add an d re lea s e s sc l r e ce iv e a ddre s s is read fro m sspb u f sc l is he ld low wh i l e ckp = 0 da t a i s re a d from sspbuf wh en sen = 1 : c k p is cl ea r e d a fte r 9 th fal lin g e dge of r ece iv ed by te s e t b y so ft w ar e , rele as ing sc l http:///
MCP19114/5 ds20005281a-page 170 ? 2014 microchip technology inc. f i g ure 28- 13 : i 2 c s l ave , 1 0 -bit addr es s, rece ption ( s en = 0 , ahe n = 1 , dhe n = 0 ) r e c e iv e f i rs t add r es s byte ua re c e i v e sec o n d ad dres s by te ua re c e i v e da t a ac k receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl sspif bf ac k d t ua ckp acktim 12345678 9 ack ack 12 34 5 6 7 8 9 12 34 56 78 91 2 cleared by software cleared by software r/w = 0 s s e t by ha r dw ar e on 9 th fa lli ng edg e slav e s o f t w a re c l e a rs ackdt to ack th e re ce iv ed b y t e sspbuf c an be read anytime before the next received cycle r e c eiv ed dat a is rea d fro m sspbuf u p date of ssp ad d , c l e a rs ua an d rel e a s es scl if whe n ahen = 1 : on t he 8 th fa lli ng edg e o f sc l of a n a ddre s s by te, ckp is cle a r e d ackt im i s s e t by ha rdware on 8 th fal lin g e dge of sc l upda te to ssp add is no t allow e d u n til 9 th fal lin g e dge of sc l se t ckp with s o f t ware r el e as es s c l http:///
? 2014 microchip technology inc. ds20005281a-page 171 MCP19114/5 f i g ure 28- 14 : i 2 c s l ave , 1 0 -bit addr es s, t rans mis s i o n ( s e n = 0 , ahe n = 0 , dhe n = 0 ) r e cei v i ng addre s s ack receiving second address byte sr r e c e iv e f i rs t add r es s by te ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ua ckp r/w d/a 12345 6789 1 2 345 6789 12345 678 9 1 2 3456 789 ac k = 1 p ack r/w = 0 s set by hardware ackstat set by hardware mas t e r se nds r es t a r t ev en t ma st er se nds no t ac k ma st e r s e nd s s t op c ond iti o n c l e a r ed by so ftw ar e sspbuf l oad ed w i th re cei v e d ad dres s ua i ndi c a tes ssp add m u s t be up date d af te r ssp add is upd ate d . ua is cleared and scl is released r e c e iv ed ad dres s is rea d fro m s spbuf h i gh add res s i s l o a ded b a c k i n to ssp ad d r/w is c o p i ed f r om th e m a tc hi ng a ddre s s by te da t a t o tra n s m i t is l oad ed in to s spbuf s e t b y s o ft w a re rel e a s es scl m a st er ? s no t a c k i s c o p i ed ind i c a te s a n ad dres s ha s b een rec ei v e d wh en r/w = 1 : ckp is cleared on 9 th falling edge of sclx http:///
MCP19114/5 ds20005281a-page 172 ? 2014 microchip technology inc. 28. 4.7 c lock s t re tching c l ock stre tc hin g oc cu rs w hen a dev ic e on th e bu s h o ld s t he sc l li ne low , ef fec t iv el y p a u s in g c om m u nic at ion . t he s l av e m ay s t retc h th e clo c k to al l o w mo r e t i me t o h a n d le da ta or p r epar e a r e s p o n s e f o r t h e ma st er de vi ce . a ma st e r d e v i c e is no t c oncern e d w i th s t ret c hi ng, as i t is stre tc hin g an yti m e it i s a c ti ve on the bu s and no t tra n s f erring d a t a . an y s t ret c hi ng don e by a s l av e i s in vi si ble to th e m a s t er s o f t w a r e a n d ha ndl ed by the ha rdw a re tha t g ene rates scl . th e ckp bit i n the sspco n 1 r egi s te r is u s ed to c ont rol s t retc hi ng i n so f t w a re . a n y ti me t he c kp bit i s c l e a red , t he m odu le w i l l w a it fo r t he sc l li ne to g o low a nd t hen ho ld it. s e tti ng c k p w ill rel eas e sc l an d a llo w mo re c o m m u n i c at ion . 28. 4.7.1 n or ma l cl oc k s t r et c h i ng fo ll ow in g a n ac k , if the r/w bi t i n th e ssp st a t re gis t er i s s e t, cau s i ng a read req ues t, th e s l av e h a rd wa re wi l l cl e a r ckp . th i s a l l o ws th e s l a v e ti m e to u pda te ssp bu f w i th da t a t o tra n s fer t o th e m a s ter . if th e sen b i t i n th e sspcon2 re gis t er is s e t, th e s l av e h a rdw a re w i l l al w a ys s t retc h th e cl oc k a f ter t he ac k s equ en ce. o n ce th e sl av e is read y , c kp is s e t b y s o f t w a r e a nd co mm un ica t io n re su me s. 28. 4.7. 2 10- b i t a d d r e s s i n g mo de in 1 0 -b it add r es si ng m ode , w hen t he u a bi t i s s e t, th e c l oc k is alw a ys str etc hed . th is is the o nl y ti me the sc l i s s t ret c h ed w i tho u t c kp bei ng cl eare d . sc l i s re lea s e d im m edi ate l y af t e r a w r ite to ss p a d d . 28. 4.7. 3 b y t e nac k i n g wh en ah en bi t in th e s spc on 3 re gi ste r i s s e t, c k p i s cl eare d by ha rdw a re af te r th e 8 th fal lin g edg e of sc l fo r a rec e i v e d m a tc hin g ad dres s byt e . wh en d h e n b i t in t h e s s p c o n 3 r e g i s t er i s s e t , c k p i s c l ea r e d a fte r th e 8 th fal lin g e dge of sc l fo r rec e i v e d da t a . s t ret c hi ng af ter the 8 th fal lin g e dge o f sc l al low s th e s l av e to lo ok at th e rece iv ed ad dre s s o r d a t a an d de ci de if i t wan t s to ack the rec e iv ed da t a . 28. 4.8 c lock s y nchr o n ization a nd th e c k p bi t an y tim e the c kp b i t is c l e a red , t he mo dul e w ill w a it fo r the sc l lin e to go lo w an d th en hol d i t. h o w e ve r , c l ea rin g th e c kp bi t w i ll not as se rt the sc l o u tp ut l o w un til t he sc l out put is alre ady sam p l e d lo w . th ere f ore, t he c kp bi t w ill not a s s e rt th e sc l l i ne u n ti l an ex te rnal i 2 c m a s t er d e v i c e ha s alre ad y a s s e rte d th e sc l lin e. th e sc l out put w i l l rem a i n low un til th e c kp b i t i s s e t and al l o t her dev ic es on the i 2 c b u s h a v e r e l e as ed s c l. t h i s e n s u r e s t h at a w r i t e t o t h e c kp bit w i l l not v i ol ate th e mi nim u m hig h tim e re qui rem ent for sc l (ref e r to fi gure 2 8 - 16 ). figure 28-15 : c lock s y nch ronization t i ming note 1 : th e bf b i t h a s n o ef fec t on w het her th e c l oc k w ill be str e tc hed or n o t. thi s i s di ffe r e nt t h an p r e v i ou s ve r s i o ns o f t he m od ule tha t w o uld no t s t ret c h the c l oc k or c l ea r c k p , if sspbuf wa s read b e fo re th e 9 th fal l i ng e dge of sc l. 2: pre v i ous ve rsi on s of the mo dul e di d n ot s t ret c h the c l oc k for a tran sm is si on if sspbuf was l o a ded b e fore t he 9 th fal lin g ed g e of s c l . i t is n o w al w a ys cl ea r e d f o r re ad requ es t s . note : pre v i ous ve rsi ons of th e m o du le d i d n o t stretch the clock if the s e c ond a d d r es s by te did no t m a tc h. sda scl dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon1 ckp master device asserts clock master device r e l e as es cl oc k http:///
? 2014 microchip technology inc. ds20005281a-page 173 mcp191 14/5 2 8 . 4 . 9 g e n er al c al l ad d r ess s u ppo r t th e ad dres si ng p r oc edu re for th e i 2 c bu s is suc h th at th e f i rs t b y te af ter the s t art co ndi tio n u s ua ll y d eter m i nes w h ic h dev ic e w ill b e the s l av e ad dres se d b y th e ma st er de vi ce. the e x c e p t ion is the g ene ral cal l a ddre s s w hi c h can ad dres s all de vic es . w hen thi s a ddre s s is u s e d , a ll devic es s hou ld, in the o ry , respon d w i th a n ac k now l edg e. th e ge nera l c a ll add res s is a res e rv ed a ddre s s in th e i 2 c pro t oc ol, d e fi ned a s a ddres s 0x0 0 . wh en th e gcen bit i n the sspco n 2 re gi s t e r i s s e t, th e s l av e m od ule w i ll au tom ati ca lly ac k t h e r e ce pt i o n of t h is a ddre s s re gard l e s s of th e v a l ue st ored i n ssp ad d . af t er the s l av e cl oc ks i n an ad dres s of a ll ze ros w i th th e r/w b i t c l e a r , a n in terru pt i s g ene rate d an d s l av e s o f t w a r e c a n rea d sspbuf an d res pon d. fi gu re 28 -17 s h o w s a ge nera l ca ll re ce ptio n s equ en ce. in 10 -bit add r es s m o d e , t h e u a bit w ill no t be s e t o n th e rece pti on of th e g ene ral c a ll a d dre s s . t h e sl av e w i l l p r ep are to re ce iv e th e s e c o nd by te as dat a, j u s t a s i t w o u l d i n 7 - bit mo de. if the ahen b i t in the sspcon3 regi s t er i s s e t, j u s t a s w i t h an y o t her add res s rec e p t io n, th e s l av e h a rdw a re w i l l s t retc h th e c l oc k a f ter t he 8 th fall in g edg e of sc l. th e sl ave m u s t the n s e t it s ac kd t v a l ue an d rele as e th e cl ock w i th co mm un ic ati on pro g res s i ng as it w o ul d no rm all y . figure 28-16 : s lav e mode g e ne ral call ad dres s se quence 28. 4.10 ss pm sk 1 r e g i s t er an ssp m a s k (sspm sk1) reg i s t er is av ail abl e in i 2 c sl av e mo de a s a m a s k fo r the v a l ue h e ld in th e sspsr reg i s t er duri ng an ad dre s s c o m p ar is o n o pera t io n. a ze ro (? 0 ?) bit in the sspm sk1 re gis te r ha s th e ef fec t of m a k i ng t he c o rres p o ndi ng b i t of th e re ce ive d a ddre s s a ?don ?t care ?. th is re gis t e r i s res e t to al l ? 1 ? s up on an y r e s e t c ond iti on a nd, th ere f ore , has no ef fe ct on st a nda rd ssp ope rati on u n ti l wri tten with a m a s k v a lue . th e sspm sk1 regi s t er i s a c ti v e du ring : ? 7 -bit addr ess m ode : a ddres s c o mp are of a<7:1 > . ? 1 0-bi t add r es s m ode : ad dres s com p a r e o f a<7: 0> o n ly . the ssp m a s k h a s no ef fec t du rin g th e re ce ptio n o f th e fi rst (hig h) b y te of the add res s . sda scl s sspif bf (sspstat<0>) cleare d b y s o f t w are sspbuf is rea d r/w = 0 ack general call address r e ce iv ing d a t a ack 12 3 4 5 6789123456789 d7 d6 d5 d4 d3 d2 d 1 d0 gcen (sspcon2 < 7>) ?1 ? a d dr e s s is co mpar e d to ge ne r a l c a ll a d d r es s a fte r a c k , set interrupt http:///
MCP19114/5 ds20005281a-page 174 ? 2014 microchip technology inc. 28. 5 i 2 c master mode m a s t er m o d e is en abl ed b y s e tti ng a n d cle a ri ng th e a ppro p ri ate sspm b i t s in the ss pco n 1 re gis t er an d b y s e tti ng the ss pen bit. in m a s ter m o d e , th e sd a an d sc k pi ns mus t be con f ig ure d as i n p u t s . the m ssp p e rip her al h a rd w a re w i ll ov erri de the out put dri v er tr is c ont rols wh e n n e c e s s ary , to driv e the pin s l o w . th e ma ste r mod e of op erat ion i s su ppo rted b y in terru pt ge n e r a t i o n on t h e de t e ct io n of t h e s t a r t an d s t op c ond iti ons . t he s t o p (p) a nd s t a r t (s) b i t s are cl eare d fro m a res e t o r when the m ssp m o d u l e is di s a ble d . c o ntrol o f th e i 2 c b u s m a y be t a k e n w h e n t he p bi t i s s et or th e b us is idl e. in fi rmw a r e -c on trol led ma ste r m ode , us er cod e c ond uc t s al l i 2 c bu s ope rati ons b a s ed on s t art an d s t op bit con di t ion det ec tion . s t art a nd s t o p co nd itio n d etec t i on is the o nl y ac tiv e c i rc uit r y in t his mo de. al l o t her c om m uni ca tion is don e by the u s e r ? s s of t w a re d i rec t ly m a n i pu lat i ng the sd a an d sc l li nes . th e fo llo wing e v e n t s will c a u s e t he ssp in terru pt fla g b i t (ssp if) to be s e t (ssp i n te rrupt , if ena bl ed): ? s t ar t co ndi tio n d ete cte d ? s t o p c on di t i on de t ec t ed ? d a t a tr ans fer byt e tra n s m i tted / rec e i v ed ? a ck no w l ed g e t r an s m i t t e d/ r e ce i v e d ? r e pea ted s t art g ene rate d 28. 5.1 i 2 c m a ste r m o d e o per a t i o n th e m as t er de vic e gen erat es al l o f th e s e ri al cl oc k pu ls es a nd th e s t art an d s t op co nd itio ns . a t r ansfer i s en de d w i th a s t op co ndi tio n or w i th a r epe ate d s t a r t c ond iti on. si nc e the r e pea ted s t a r t co ndi t io n is a l s o th e b egi nn ing of the ne xt se ria l tr ans fer , th e i 2 c b u s wi l l n ot be r el e as ed . in m a s t er t r an sm it mo de, s e ria l dat a i s ou tput th roug h sd a, w h ile sc l ou tput s th e s e ria l c l oc k. t he f i rs t by te t r an sm it t e d c o n t ai n s t h e s l a v e a d d r e s s of t h e r e ce i v i n g de vi ce (7 b i t s ) and t he r e a d /w rite (r/w ) b i t. in t h is case, the r/w bi t w ill b e lo gic ? 0 ?. s e r i al d ata is tra n smi tted 8 bi t s at a tim e . af te r e a ch b y te i s tra n s m i tted , a n acknow l edg e bit is re ce iv ed. s t art an d s t o p co nd i t i o ns a r e o u t pu t t o in di c a t e t h e b e g i nn i n g an d t he e n d of a s e ria l tra n s f er . in ma ste r rec e i v e mo de, the firs t by te trans m itted c ont ain s the s l av e add res s of the tra n s m i tting dev i c e (7 bit s ) and th e r / w bit. in this case, the r/w bit w i l l b e l ogi c ? 1 ?. thu s , the fi rst by te t r ans m i tte d i s a 7 - bit sl av e ad dre s s fo llo w ed by a ? 1 ? to ind i c a te the rec e i v e bi t. se rial d a t a i s re cei v e d vi a sd a, w h il e sc l ou tpu t s th e s e ria l c l o c k . seri al d a t a is rec e iv ed 8 bi t s at a t i m e . af t e r ea ch by te is rec e i v e d , an ack n o w led ge b i t i s tra n s m i tted . s t art an d s t op c ond iti ons in dic a t e th e be gi nni ng and en d of tran sm is si on. a bau d r a te g ene rato r i s us ed to s e t th e cl oc k fre que nc y o u tpu t on sc l . refe r to se ction 2 8 . 6 ? b aud rate g e nerato r? fo r m o re det ail s . 28. 5.2 c lo ck a r bit r a t io n c l o c k ar bitra t io n o c c u rs w h e n th e m a s t er , dur ing an y re cei v e , tra nsm it or r ep eat ed s t a r t/s top co ndi t io n, r el e as es t h e s c l pi n ( s c l al l ow e d t o f l o a t hi g h). when th e sc l pin is al low e d to flo a t h i gh , th e bau d r a te g e n e rat o r (br g ) i s su sp end ed fro m c oun tin g un til th e sc l p i n i s ac tua l l y sa mp le d hig h . wh en t he sc l p i n i s s a m p le d hig h , the bau d r a te g ene rato r is relo ade d w i t h the co nten t s o f ssp ad d < 7:0 > and beg in s c oun tin g . t h is en su res tha t th e sc l hig h t i me w i l l al w a y s be at le ast on e br g roll ov er cou n t in the e v e n t th at the cl oc k i s hel d l ow b y an ex terna l dev i c e ( fi gu re 28 -17 ). note 1 : th e m ssp m o dul e, wh en c onf igu r ed i n i 2 c m a s t e r m ode , d oes n o t al low que uin g of ev ent s. f o r in st a n c e , th e us er i s n o t a llo w ed to ini t ia te a s t a r t c on dit ion an d i m m e d i ate l y wri t e th e sspbuf regi s t e r to i n iti a te t r ansm i ss io n bef ore th e s t art c ond iti on is c om ple te. in thi s ca se , th e sspbuf wil l n o t b e wri tten to an d th e w c o l bit w ill be set , in dic a ti ng tha t a wri te to th e sspbuf did no t oc c u r . 2: w hen in m a s t er m o d e , s t art/ s t o p d e tec t i on i s ma sk ed and an int e rrup t i s g ene rate d w h en the sen /pen bi t i s c l ea red an d th e ge ne rati on i s comp l e te . http:///
? 2014 microchip technology inc. ds20005281a-page 175 mcp191 14/5 figure 28-17 : baud rate ge ner ato r t i m i ng wi th cl ock arbi tration 28. 5.3 w c o l s t a t us f l ag if t he u s er wri t es the sspbuf when a s t art, re s t a r t, s t op , r e c e i v e or t r ansm i t s e q uen ce is i n p r ogre s s , th e w c o l is s e t an d the c ont ent s of the bu f f e r a r e u n ch an ged (the w r i t e d oes no t oc cu r). any tim e th e w c ol bi t is s e t, it i n d i c a tes th at a n a c t i on on sspbuf wa s a ttem p te d wh ile the m odu le w a s not id l e . 28. 5.4 i 2 c m a s t er m o de s t ar t condition t i m i ng t o in itia te a s t art c ond iti on, th e us er se t s th e s t art en abl e b i t, se n , in the sspco n 2 reg i s t er . if th e sda a nd sc l p i ns are s a m p l ed h i gh , the ba ud r a te g e n e rat o r is re lo ade d w i th th e co nte n t s of ssp ad d < 7: 0> a nd s t art s i t s c o u n t. i f sc l an d sd a a r e bo th s a m p le d h i gh when the ba ud r a te g e n e ra tor ti me s out (t br g ) , t h e s d a pi n i s d r iv en lo w . t h e a c t i on of t he sd a be ing driv en low w h i l e sc l i s h i gh i s th e s t art c o n d it ion and c a u s e s th e s bi t in t h e sspst a t 1 re gis t er to be s e t. f o ll ow in g th is, the ba ud r a te ge ne r a to r i s r e l o ad ed w i t h t h e c o n t en ts o f ssp add < 7:0 > an d res u m e s i t s c o u n t. wh en th e bau d rat e gen e ra tor t i m e s ou t (t br g ), th e s e n bi t in th e sspcon2 regi s te r wi ll be au tom a ti c a lly c l e a red b y ha rdw a re; th e ba ud r a te g e n e ra tor i s s u s p en de d, l eav in g th e sd a l i n e he ld low and the s t art co ndi t io n i s co mp l e t e . figure 28-18 : f irs t s t ar t bit t i m i ng sda scl dx ? ? 1 dx 0 3 h 02h 01 h 0 0h ( hol d o f f) 0 3 h 0 2 h scl allowed to tr ans iti on hig h sc l de as se rted but sl av e h old s sc l lo w (c loc k arbi trati o n ) b g r d e c r em ent s o n q2 a n d q4 cy cl es brg va l u e brg re l o a d s c l is sa mp le d hi gh , r e l o ad t a k e s pla c e an d br g s t art s i t s c o u n t note : because q ue uin g of ev en t s is not a llo w ed, w r i t ing to th e low e r 5 bi t s i n the ss pc o n 2 re gis t er is d i s abl ed un til th e s t a r t c o n d iti o n is co mp le t e . note 1 : i f , a t t h e be gi n n i n g of t h e s t ar t co nd i t i o n, th e s d a an d sc l p i ns a r e alre ady s a m p le d low , o r i f, duri ng th e s t a r t c ond iti on, t he sc l l i ne is s a m p l ed l o w be fore the sd a l i ne is dri v e n lo w , a bus c o ll is ion oc cu rs, the bus c o l lis io n in terru pt f l ag , bcl i f , is se t, t he s t a r t c ond iti on is abo rted a n d the i 2 c m odu le is r e set in to i t s id l e s t at e. 2: th e phil ip s i 2 c s p ec if i c a t io n sta t es t h at a bu s col l i s i on c an not oc cu r on a s t art . sda scl s t brg 1 st bit 2 nd bi t t br g sda = 1 , scl = 1 w r ite to sspb u f oc c u rs h e re t brg t brg writ e to sen b i t occ u rs he re set s bit (sspstat<3>) at c o m p l e tio n o f s t art bit , ha rdware c l ea rs sen bit an d s e t s sspif bit http:///
MCP19114/5 ds20005281a-page 176 ? 2014 microchip technology inc. 28. 5.5 i 2 c m a s t er mode rep e a t ed s t a r t condition t i m i ng a r epe ate d s t art c ond iti on oc curs w h en the r sen b i t i n the sspco n 2 re gis t er is pr ogra m m e d hi gh an d th e m as t er s t at e ma ch ine is n o lo nge r ac tiv e. wh en th e r sen b i t i s s e t , the sc l p i n is as se rted low . whe n th e sc l pin is sa mp le d lo w , th e ba ud r a te g e n e ra tor i s l oad ed a nd be gi ns c o u n tin g . th e sd a pin is re le ase d (b roug ht hi gh) fo r one ba ud r a te g ene rato r c o u n t (t br g ). whe n the ba ud r a t e ge nera t or ti me s ou t, if sd a is s a m p le d h i g h , t he sc l pin w i l l be dea ss erte d (b roug ht hig h ). w hen sc l is sa mp led hi gh, the bau d r a te g ene rato r i s rel o a ded a nd b egi ns c o u n tin g . sd a a nd sc l m u s t be s a m p le d hig h for o ne t br g . thi s a c ti on is the n fo llo w ed by as se rtion of the sd a pi n (sda = 0 ) for on e t br g w h il e sc l is hi gh . sc l i s as se r t ed l ow . f o ll ow in g th i s , t he r s e n b i t i n the sspcon2 re gis t e r will be auto m a t ic al ly c l eare d an d th e bau d r a te ge ne rator w i ll n o t b e rel oad ed, l e a v in g th e sd a pin h e ld lo w . as s oon as a s t art co ndi tio n i s d e tec t e d o n the sd a a nd sc l pin s , the s bit in th e sspst a t re gi s t e r wil l b e s e t . th e sspif b i t will n o t b e s e t u n ti l th e ba ud r a te ge ner ator has ti me d ou t. figure 2 8 - 1 9 : r e peat s t a r t condition w a ve form note 1 : if r sen is p r og ram m e d w h il e any oth e r ev en t i s in p r ogres s , it w ill n o t t a k e ef fec t . 2: a bu s c o l lis io n du ring the r e pea ted s t a r t c ond iti on occ u rs i f: ? s d a i s s am pl e d lo w w h e n s c l go es fro m l o w to hi gh. ? s c l goe s l o w bef o re sd a i s as se rted l ow . thi s m ay i ndi ca te tha t ano the r m a s t er is atte mp tin g to t r an s m i t a da ta ? 1 ?. sda scl repeated start w r i t e to sspbuf occurs here 1 st bi t s bit set by hardware t br g t br g sda = 1 , sda = 1 , scl (no ch ang e) scl = 1 t brg t br g t brg sr w r ite to sspco n 2 o c c u rs he re at c o mp le tion of s t art b i t, hard w are cl ears r sen bi t and s e t s sspif http:///
? 2014 microchip technology inc. ds20005281a-page 177 mcp191 14/5 28. 5.6 i 2 c m a s t er mode t r a n sm is si on t r a n s m i s s i on of a d a t a by te, a 7 - bit ad dres s or th e o t her ha lf of a 10 -bi t a ddre s s is ac c om pli sh ed by s i m pl y writing a v a lu e t o t he sspbuf regi s t e r . thi s ac t i on wil l s e t th e buf f e r full (bf) fl ag b i t a nd a llo w t he ba ud r a te g e n e rat o r to be gin co unt ing an d s t art the nex t tra n s m i s s i o n . ea ch bi t o f ad dre s s / da t a w i ll be sh if te d o u t o n to th e sd a pi n a f ter the fa lli ng ed ge of sc l i s as se r t ed . s c l i s he ld l o w f o r on e b a ud r a t e ge ne r a t o r ro llo v e r c o unt ( t br g ). d a t a s hou ld b e v a li d b e fore sc l is r e l e as ed h i g h . w h en t h e s c l pi n is r e l e as ed h i g h , i t i s he ld t hat w a y fo r t br g . t h e d a ta on t h e s d a pi n mu st re ma in st a bl e f or th at dur atio n and s om e h old ti me af ter th e nex t fal lin g edg e of sc l. af te r th e 8 th bit i s sh if te d ou t ( t h e fa l l i n g ed ge o f t h e 8 th c l o c k ) , the bf fl ag i s c l e a red and t he m a s t er re lea s e s th e sd a. thi s a llo w s th e s l a v e dev ic e b e i ng add res s ed to res pon d w i th a n ack bi t du ring the 9 th bit ti me if an add res s m a tc h o c c u rre d o r if data was received properly. the status of ack i s writ ten into the ackst a t b i t on the ris i ng edg e o f t he 9 th cl oc k. if th e ma ste r re ce iv es an ac k now l edg e, th e ac kn ow le dge s t a t us bi t (ac kst a t) i s c l e a red . if n o t, t he b i t is set . af te r th e 9 th c l o c k , th e sspi f bi t is s e t a nd the ma ste r c l oc k (baud r a t e g e n e rat o r) i s s u s pen ded un til the n e x t da t a b y te is loa d e d in to th e sspbuf , le av ing scl low an d sda unc ha nge d ( f i gu re 2 8 -20 ). af t e r t he wri t e to t he sspbuf , eac h b i t of t he add res s w i ll b e s h if t ed o u t o n the fal lin g e dge of sc l u n ti l al l s e v en a ddre s s bit s an d th e r / w bi t are com p l e te d. o n th e fal l i ng e dge o f the 8 th cl oc k, th e m ast er w i l l rel eas e th e sd a pin , al low i ng the sl av e to res p o nd w i th a n ac kn ow le dge . o n the fal lin g e dge of the 9 th cl oc k, t h e m a s t er w ill s a m p le th e sd a pin to se e i f t he add res s w a s rec ogn iz ed by a s l a v e. th e st atus of the ac k bit i s l oad ed i n to th e ackst a t s t at us b i t in t he sspcon2 re gis t er . foll ow i ng the fall in g edg e of th e 9 th cl oc k tra n s m i s s i o n o f th e a ddr es s , the sspif is s e t, the bf fl ag is cl ea red and the bau d r a te g e n e ra tor i s t u rne d o f f unt il ano the r wri t e to t he sspbuf t a k e s pl ac e, h o ld ing sc l l o w a nd all o w i n g sd a t o fl oat. 28. 5.6.1 b f s t atu s f l ag in t r a n s m i t m o d e , the bf b i t in th e sspst a t reg i s t er i s s e t when t he cpu write s to sspbuf a nd is c l eare d w h en a ll 8 b i t s are sh if t ed o ut. 28. 5.6. 2 w co l s t a t us f l a g if the us e r write s t he s spbuf whe n a t r ans m it i s al rea d y in p r ogre s s (i. e ., sspsr i s s t il l s h if ting ou t a da t a by te), the wc o l i s s e t and th e c ont ent s o f th e bu f f e r a r e un ch ang ed (the w r ite do es not oc cu r). w c ol mu st b e cl ea r e d b y so f t w a r e be f o r e t h e n e xt t r an sm is si o n . 28. 5.6. 3 a c k s t a t s t a t us f l a g in t r a n s m i t m o d e , the ackst a t bit i n t h e sspcon2 re gist er is cle a re d w h e n th e s l av e h a s se nt a n ac kn ow le dge (ac k = 0 ) an d i s set when the slave does not acknowledge (ack = 1 ) . a sl av e se nd s an ac kn ow le dge w h e n it ha s re co gni ze d i t s a d d r es s (i ncl u d i ng a gen eral c a ll ) or w hen th e s l a v e ha s pr ope rly rec eiv ed it s d at a . 28. 5.6. 4 t y p i c a l tr an sm it sequen ce : 1. th e u s e r ge ne rates a s t art co ndi tio n b y se ttin g th e sen b i t i n t he ss pc on 2 regi st er . 2. sspif is s e t b y ha rdware on c o m p le tio n of th e st a r t . 3. sspif is c l ea red by s o f tware . 4. th e m ssp m o dul e will wa it the req u ire d s t a r t ti me be fore any ot her ope rati on t a k e s pla c e . 5. th e u s e r l oad s t he sspbuf wi th the s l av e ad dre s s to tran sm it. 6. ad dres s is s h i f ted o u t the sd a p i n un til al l 8 bit s ar e tran sm itt ed. t r a ns m i s s i on beg ins as s oo n as sspbuf is writt en t o . 7. th e m ssp m odu le s h if t s in th e ack bi t f r om th e s lav e d e vi ce and w r ite s it s v a lu e in to th e ackst a t bi t in the sspcon2 re gis t er . 8. th e m ssp m o dul e g e ne rate s an int e rrup t a t th e en d of the 9 th c l oc k c y c le b y s e t t ing th e sspif bi t. 9. th e us e r l oad s the sspbuf wit h e i g h t bit s of da t a. 10 . d at a i s sh if te d out the sd a pin un til al l 8 b i t s a r e tra n s m i tted . 1 1 . th e m ssp m odu le s h if t s in th e ack bi t f r om th e s lav e d e vi ce and w r ite s it s v a lu e in to th e ackst a t bi t in the sspcon2 re gis t er . 12 . s tep s 8 ? 1 1 are r epe ate d fo r al l tra n s m i tted dat a by te s. 13 . t h e us er g ene rate s a s t o p or r e st a r t co ndi t io n by s e tti ng th e pen or r sen bi t s in t h e sspcon2 regi s te r . inte rrupt is g ene rate d o n c e th e s t op /res t a rt co ndi tio n i s c o m p l e te. http:///
MCP19114/5 ds20005281a-page 178 ? 2014 microchip technology inc. f i g ure 28- 20 : i 2 c mas t er mode w a v e f orm (t rans mi ss ion, 7 or 1 0 -bit ad dres s ) sda scl sspif bf ( sspst a t < 0 >) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack r/w = 0 t r an sm it a d dr e s s t o s l a v e 1 2 345 6 7 8 9 1 2 34 5 6 7 8 9 p sspbuf is wri tten by s o f t ware af ter s t a r t c ond iti on, sen c l ea red by hard w are s sen = 0 write sspcon2<0> sen = 1 start condition begins cleared by software sspbuf writte n pen r/w cleared by software fro m s l av e , c l ea r ackst a t bi t sspcon2<6 > t r ans m i tti ng d a t a or se co nd h a lf of 1 0 -bi t ad dres s ackst a t in sspcon 2 = 1 sspbuf writt en wi th 7 - bi t ad dres s and r/w s t art tran sm it scl he ld l o w wh i l e cpu re s p ond s t o sspi f cleared by software service routine from ssp interrupt http:///
? 2014 microchip technology inc. ds20005281a-page 179 mcp191 14/5 28. 5.7 i 2 c m a s t er mode rece p t i o n m a s t er mo de rec epti o n is en ab led by pr ogra m m i n g th e re c e i v e ena b le (rcen) bi t in th e sspcon2 re gis t e r . th e bau d r a te g ene rato r b egi ns c o u n ti ng an d, upo n e ach ro llo ve r , t he st ate of the sc l pi n c ha nge s (hig h to low/low to h i g h ) and d a t a is s h i f te d into t he sspsr. af t e r t he fal lin g e dge of th e 8 th cl oc k, the rec e i v e en abl e fl ag is au tom ati ca lly c l ea red , th e c on t ent s o f th e sspsr are loa ded into the sspbuf , the b f flag bit i s s e t, th e sspif fl ag bi t is s e t an d the baud ra te g e n e rat o r i s su sp end ed from c o u n ti ng, ho ldi ng sc l l o w . th e mssp i s no w in id le s t a t e aw a i tin g th e nex t c o m m a nd. wh en th e b u f f er is re ad by t he c p u , t he bf fl ag bi t is a u tom a t i c a ll y cle a re d. t he us er c a n the n s end an ac k now l edg e bi t at th e en d of re ce pti on b y s e tti ng th e ack n o w led ge se que nce enab le (ac ken ) b i t i n th e sspcon2 regi s t e r . 28. 5.7.1 b f s t atu s f l ag in rec e iv e op era t ion , the bf bit i s s e t w h e n an add res s o r da t a b y te is l oad ed int o sspbuf from sspsr. it i s c l e a red when th e sspbuf regi s te r is re ad. 28. 5.7.2 s s p o v s t atus f l a g in rec e iv e op era t ion , the s spov b i t is se t w hen 8 bit s a r e rec e i v ed int o the sspsr and t he bf f l ag b i t i s al r e ad y se t f r om a p r ev io u s r e c e pt i o n . 28. 5.7.3 w c o l s t a t us f l a g if the us er write s t he sspbuf wh en a re c e iv e i s a l rea d y i n pro g res s (i .e., ss psr i s s t il l sh if ti ng i n a da t a by t e) , t he w c o l bi t is s et an d t h e c on t en ts of t he bu f f e r a r e u n ch an ged (the w r ite do es not oc cu r). 28. 5.7. 4 t y p i c a l re ce iv e s equ enc e: 1. th e u s e r ge ne rates a s t art co ndi tio n b y se ttin g th e sen b i t i n the ss pc on 2 regi st er . 2. sspif is s e t b y ha rdware on c o m p le tio n of th e st a r t . 3. sspif is c l ea red by s o f tware . 4. us er wri t es sspbuf wi th t he s l a v e add res s to tra n s m i t an d th e r / w bi t s e t. 5. ad dres s is s h i f ted o u t the sd a p i n un til al l 8 bit s ar e tran sm itt ed. t r a ns m i s s i on beg ins as s oo n as sspbuf is writt en t o . 6. th e m ssp m odu le s h if t s in th e ack bi t f r om th e s lav e d e vi ce and w r ite s it s v a lu e in to th e ackst a t bi t in the sspcon2 re gis t er . 7. th e m ssp m o dul e g e ne rate s an int e rrup t a t th e en d of the 9 th c l oc k c y c le b y s e t t ing th e sspif bi t. 8. us er s e t s the rc en bit in the sspc on2 regis t er and the m a ster clo cks in a byte from the sl ave. 9. af t e r t he 8 th fal lin g e d g e o f scl , sspi f a n d bf ar e s e t. 10 . m as ter c l ear s sspif and re ad s the re c e i v e d by te from sspuf , c l ea rs bf . 11 . m a s t e r s e t s a c k va l u e sent to slave in ackdt bit in the sspcon2 register and initiates the ack by setting the acken bit. 12. masters ack is cl oc ke d ou t to t he sl av e an d sspif is s e t. 13 . t h e u s e r c l ears sspif . 14 . s tep s 8?1 3 are rep eat ed for ea ch re cei v e d by te fro m the sl ave . 15 . m as ter s end s a no t ac k or s t op t o e nd co mm un i c a t io n. note : th e m ssp m odu le m u s t be i n a n id le s t at e befo r e the r c e n bit i s se t or the rcen b i t wi l l b e d i sre g a rd e d . http:///
MCP19114/5 ds20005281a-page 180 ? 2014 microchip technology inc. f i g ure 28- 21 : i 2 c mas t er mode w a v e f orm (rec ep tio n , 7-bit ad dres s ) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sd a sc l 12 3 4 5 6 78 9 1 2 3 4 5 6 7 8 9 1234 ack receiving data from slave rec e iv ing dat a f r om s lav e d0 d1 d2 d3 d4 d5 d6 d7 ac k r/w ss pi f bf ac k is not sent write to sspcon2<0> (sen = 1 ), ack from slave dat a shif t ed in on f alli ng edge of clk cleared by s o f t ware sen = 0 ssp o v (s sps t a t < 0> ) ack cleared by sof t ware cleared by s o f t ware ac k en begin start condition cleared by so f t ware rcen w r it e to s s p b uf oc curs here, s t ar t xm i t mast er conf i g u r ed as a receiv er by pr ogram ming s s p c o n 2<3> (r cen = 1 ) rc en cleared aut om at ically w r it e t o ss pco n 2<4> t o st art a cknowledge sequ ence sd a = a c kd t (ss p c o n 2 < 5 > ) = 0 a c k fr om mas t er sd a = ac k d t = 0 rce n = 1 , s t a r t next rec e ive s e t ack e n, s t ar t ack n owledge s equence sd a = ac k d t = 1 rce n c l ear ed a u to m a ti c a ll y pe n bi t = 1 wr it te n h e r e bus m a st er te r m i n a te s t r ansf er sd a = 0 , scl x = 1 while c p u res ponds t o ss pxi r s e t ss pi f i n te r r u p t at end of receive s e t ss pi f i n te r r u p t at end of ack nowledge sequenc e s e t ss pi f at end of re ceive c l ear ed in so f t w a r e se t s spi f in t e r r u p t at en d of a ckno wled g e se que nce set p bi t ( s sp st a t < 4 > ) a n d ss pi f last bit is shif t ed int o ss ps r and cont ent s ar e unloaded int o ss pb uf ss po v is set beca use s s p b uf is s t ill full m a st e r c onf igured as a r e ceiver by program ming s s p c o n 2<3> (rce n = 1 ) rc en cleared aut oma t ically ac k f r om mast er sd a = ac k d t = 0 rce n c l eare d aut o m a t i c a ll y http:///
? 2014 microchip technology inc. ds20005281a-page 181 mcp191 14/5 28. 5.8 a ck now l e d g e s e que nce ti m i n g an ackn ow le dge seque nce is e nabled by s e tting the ack now ledge sequenc e e n a b le (a c ken ) bit in the sspc o n 2 r e gister . when this bit i s set, the s c l pi n is pul led l ow and the c ontent s of the acknow ledg e dat a bit are presented on the sd a pin . if the us er w i shes to gen er a t e an ack now ledge, then the ac kd t bi t s hould be cleared. if not, th e user s hould se t the ac kd t bit before st arting an ac know ledge s equenc e. the baud r a te g enerator then count s for on e rollov e r period (t br g ) and the s c l pi n is de asserted (pul led high). when the sc l pin is sam p led high ( c lock arbitration), the b a u d r a t e gene r a tor c ount s for t br g . the sc l pin is then pull ed lo w . follow i ng this, the a c ken bit is autom atical ly clea r e d , the baud r a te g enerator is turned of f and the m ssp m odule then goes into idle m ode ( f i gu r e 2 8 - 22 ). 28. 5.8.1 w c o l s t a t us f l a g if t he us er wri t es t he sspbuf wh en an ac k nowl edg e s equ en ce is in p r og res s , w c ol is se t an d th e c ont ent s o f the b u f f e r are u n c han ged (the w r i t e do es n o t oc c u r). 28. 5.9 s top condition t i m i ng a s t op bi t is a s s e rte d on th e sd a p i n at th e end of a re cei v e /tra n sm it by set t in g t he s t op seq uen ce en abl e bi t, pen, i n the sspcon2 reg i s t er . at the en d of a re cei v e /tra n sm it , t he sc l lin e is h e ld l o w a f te r th e fa lli ng ed ge of the 9 th c l oc k . w hen th e p e n bi t i s se t, th e ma st er w ill as ser t the sd a li ne l o w . wh en t he sd a l i ne is s a m p l ed low , th e ba ud r a te g ene rato r i s re loa ded and c o u n t s dow n t o ? 0 ? . w hen the ba ud ra te ge ne r a to r t i me s o u t , t h e s c l pi n w i l l be b r ou g h t h i gh an d th en, one t br g (ba u d ra te gene rato r roll ov er c oun t) late r , the sd a pin w i ll be de as se rted . w h en th e sd a pi n is s a m p l ed hi gh w h i l e sc l i s hi gh, t he p bit i n th e sspst a t reg i s t er , is s e t . a t br g l a te r , th e pen b i t i s c l e a red an d th e sspif bi t is s e t ( f i gu re 2 8 -23 ). 28. 5.9. 1 w col s t a t us f l a g if the us er w r ites th e s spbuf whe n a s t op s e que n c e i s i n pr ogre s s , th e wc o l bit is se t an d t he c o n t en t s of th e b u f f e r a r e u n ch an ged (the wr ite do es not oc cu r). figure 28-22 : acknow l edge se quen ce w a v e form figure 28-23 : s top cond ition re ceiv e o r t rans mi t mode sda scl acken au tom a t i c a ll y c l e a red t brg t brg 8 d0 9 sspif ack ac kn ow le dg e s equ enc e s t a r t s here , writ e to sspcon2 acken = 1 , ackdt = 0 sspif s e t at the end of rec e iv e cl e a re d i n so ft war e cl e a re d i n so f t w a r e sspi f s e t a t the en d of a c k n ow l e dg e s eq u en c e note : t br g = o ne ba ud r a te ge ner ator peri o d . scl sda sc l b r ou ght hig h after t brg t brg t brg t br g ack p t br g w r i t e to sspcon2, s e t pen fal lin g e dge of 9 th cl o ck scl = 1 fo r t br g , fo llo wed b y sda = 1 fo r t br g af ter sda s a m p l e d hig h . p bit (sspst a t <4> ) is s e t. pen bi t (sspcon2<2 > ) i s c l e a red by ha rdware an d th e sspif bi t is s e t no t e : t br g = one bau d rat e gen e rato r pe rio d . http:///
MCP19114/5 ds20005281a-page 182 ? 2014 microchip technology inc. 28. 5.10 sl ee p o p er at io n w h il e i n sl eep mo de , the i 2 c s l av e m o d u l e c an rec e iv e a ddres s e s o r dat a and , w h en a n add res s m a tc h or co mp l e t e by te t r an s f e r o ccu r s , wa ke t h e p r oc es so r fro m slee p (i f th e m ssp in terru pt i s ena ble d ). 28. 5.1 1 ef f e ct s o f a re s e t a res e t di s a b l e s the m ssp m o dul e and te rm i n a tes th e c u rre nt t r ans fer . 28. 5.12 mul t i- m a s t er mo de in mu lti- mast e r m o d e , th e in terru pt ge nera t io n on th e d e tect i on of th e s t a r t and s t op c o n d it ion s all o w s th e d e ter m i nation o f w hen t he b u s i s fre e . th e s t op (p) an d s t ar t (s) bit s a r e cl ea red fro m a r e s e t or w h en th e m sspx m odu le is d i s abl ed. con t rol o f th e i 2 c b u s m a y b e t a k en when th e p bi t i n the sspst a t reg i s ter is s e t or the bu s i s i d le , w i t h bo th t he s and p bi t s cl ear . whe n th e bu s i s b u s y , en abl ing the ssp in terru pt wil l g ene rate the in terru pt w h en t he s t o p c o n d iti o n oc cu rs. in mu lti- mas t e r o p e r atio n, th e sd a lin e m u st b e m o n i tor ed for arb i tra t io n to se e if the s i gn al l e ve l is th e e x pe ct ed o utpu t le ve l. th is c he c k is perf orm ed b y h a rdwa re wi th th e re su lt p l ac ed in the bclif bi t. th e s t at es w here arb i tra t io n c an be l o s t ar e: ? a d d res s t r ans fe r ? d ata t r an sf e r ? a s t ar t co nd i t i o n ? a r e pea ted s t art c o ndi tio n ? a n ack no w led ge c o nd itio n 2 8 . 5 . 1 3 m ul ti -m a s t e r com m u n i ca t i on , bu s c o lli si o n an d bu s ar bitr ation m u lt i-m a s t er m ode s u p port i s ac hi ev ed by bu s ar bitr atio n. w hen the ma ste r ou tpu t s a dd r ess / d at a bit s on to the sd a pi n, a r bit r ati on t a k e s pl ace w h e n th e m as t er ou tpu t s a ? 1 ? on sd a, by l e tti ng sda fl oat h i g h , an d ano the r m as t er as se rt s a ? 0 ? . w he n t h e s c l p i n fl oat s h i gh , da t a s ho uld be st a bl e. if the ex pec t ed dat a on sda i s a ? 1 ? a nd t h e da ta s a mp le d on t h e sd a pi n is ? 0 ?, a b u s co ll i s i o n ha s ta ke n p l a c e. t h e ma st e r wi l l se t th e bus c o ll is ion i n ter r upt f l ag (b c l if) an d res e t th e i 2 c po rt to it s id le st ate ( f i gu r e 2 8 - 24 ). if a tran sm it w a s i n pro gres s w h en t he b us c ol lis io n oc c u rred , th e t r ans mi ss io n i s hal ted, the bf fla g i s c l ea red , the sd a an d sc l l i n e s are d e a s s e rte d an d th e sspbuf c a n b e wri tten to . wh en the us er s e r v ic es th e bu s c o ll is ion in terru pt serv ic e r outi n e an d if the i 2 c bu s i s fre e, th e us er c an res um e co mm un ic ati on b y as s e rti ng a s t art co ndi tio n . if a s t art, r epeated s t art, s t o p or ack now ledge co ndition w a s in p r og r e s s w hen the bus collis ion oc curred, the co ndition is aborted, the s d a and sc l line s are deasse r t ed and the res pective c ontrol bit s in the s spc on 2 regi ster are c l eared. w hen the user se r v ices the bus coll ision i n t e r r upt s e rv ice r outine and if the i 2 c bus i s fr e e, t h e user can res ume co mmuni cation by asserting a s t art condition . the mast er w i ll continu e to monito r the s d a and sc l pins. if a s t o p condi tion occurs, the ss pi f bit w ill be set. a write to the s spbuf w i ll s t ar t t he tra n s m i s s i on of da t a at t he f i rs t da t a b i t, rega rdl e ss o f w h e r e th e tra n s m i tter lef t of f whe n th e b u s co lli si on oc cur r ed. in m u l t i-m a s t er m o d e , th e int e rrup t gen era t io n on th e de tec t io n o f s t art an d s t op c ond iti ons al low s th e de term in ati on o f w h e n th e bu s i s fre e . c o n t rol of t he i 2 c bu s c a n be t a k e n whe n the p b i t is s e t in the sspst a t re gis t er , or t he bus is id le and the s a nd p bit s a r e cl e a r e d. figure 28-24 : bus collision t i mi ng fo r t rans mit a nd ackn o w led g e sda scl bclif d a t a c h a nge s w h ile sc l = 0 sd a li ne pul led lo w by an othe r s ourc e sda re lea s e d by m a s t er sam p l e sda. whi l e sc l is hi gh , da t a d oes n o t m a tc h w h at is driv en by th e m a s t er . bus c o ll is ion ha s o c c u rre d. se t bus col l i s io n in terru pt ( b clif) http:///
? 2014 microchip technology inc. ds20005281a-page 183 mcp191 14/5 28. 5.13 .1 bu s c o ll is i on du r i ng a s t ar t c o n d it ion d u ring a s t a r t c ond iti on, a b u s col l i s i on o c c u rs if : a ) sd a o r sc l a r e s a m p l ed low a t th e b egi nni ng of th e s t a r t co nd itio n ( f i gu re 2 8 -25 ) b ) sc l is s a m p l ed l o w be fore sd a is as se rted low ( f i gu re 2 8 -26 ) d u r i n g a s t ar t co nd i t i o n, bo t h t h e s d a an d t h e s c l p i ns are m oni tore d. if the sd a p i n is al read y low or t he sc l pi n is alr ead y l o w , a ll of t he f o ll ow in g o c c u r: ? t he s t ar t c on di t i on is ab or t e d ? th e bcl i f fl ag is se t an d ? t he m ssp m o d u le is res e t to i t s idl e s t at e ( f i gu re 2 8 -25 ) th e s t art co ndi tio n be gin s w i th th e sd a an d sc l pin s d eas se rted. w hen t he sd a p i n is samp l e d hi gh , th e ba ud r a te g e nera t or i s l o a ded and co un t s d o w n . if th e sc l p i n i s s a m p le d lo w w h ile sd a i s h i gh , a bu s c o l lis io n o c c u rs b e c aus e it is as su me d that an oth e r m a s t er is att e mp tin g to d r iv e a dat a ? 1 ? d u ri ng the s t art c ond iti on. if the sda pi n i s s a m p l ed l o w d u rin g t h is c o un t, th e br g is res e t a nd t he sd a l i ne is as sert ed e a rl y ( fi gu re 28 -27 ). if, h o wev e r , a ? 1 ? i s s a mp le d o n t h e s d a p i n , t h e s d a pi n i s asse r t ed lo w at th e e n d of t h e b r g c oun t. the bau d r a te ge ne rator is th en rel oad ed an d c oun t s do w n to ze ro; if the sc l p i n is s a m p l e d as ? 0 ? d u r i ng t h is t i me , a bu s co l l i s i o n d o e s n o t oc cu r . a t t h e en d o f th e br g c oun t, th e sc l pin is as s e rte d lo w . figure 28-25 : bus collisi o n d uri ng a st art c o nd ition (sda o n l y ) note : th e re as on w hy bu s col l i s i on is no t a f a c t or d u r i n g a s t a r t co nd i t i o n i s t h at n o tw o bus m a s t ers ca n a s s e rt a s t art c ond iti on a t the e x ac t s a m e tim e . t h e r e f o r e , on e ma st er w i l l al w a ys as se r t sd a be fore t he ot her . t h is co ndi tio n do es no t c aus e a b us co lli si on b ec aus e th e tw o m a s t ers mus t be a l l o w e d to arbi trate the fi rst a d d r ess fo llo wing the s t a r t c o nd iti o n. if the add res s i s th e s a m e , a r bi trati o n m us t be a llo w ed to con t in ue i nto t he da t a po rtio n, r e pea ted s t art o r s t op c ond iti ons . sda scl sen bclif s sspif sd a go es lo w bef ore the sen bi t is s e t. set bclif , s bi t a nd ss pif s e t b e c aus e sda = 0 , scl = 1 . se t sen, e nab le s t art c o n d it ion if s d a = 1 , scl = 1 sen c l ea red a u to ma tic a l l y b e c aus e of bus c o l lis io n. ssp m o dul e re s e t in to id le s t a t e. sd a sa mp led lo w be fore s t art co ndi tio n . se t bcl i f . s b i t an d sspi f s e t bec au s e sda = 0 , scl = 1 . sspif a nd bc l i f are c l e a re d by s o f tw a re sspif and bclif are cl ea red by so f t w are http:///
MCP19114/5 ds20005281a-page 184 ? 2014 microchip technology inc. figure 28-26 : bus collision d uring s t art conditi o n ( s cl = 0 ) figure 28-27 : brg re se t due to sd a arbitration during s t art condi t i o n sda scl sen t brg t brg sda = 0 , scl = 1 bclif s sspif ? 0 ? set sen , en abl e s t a r t se que nc e i f sd a = 1 , scl = 1 scl = 0 b e fo re sda = 0 , b u s co lli si on oc curs . se t bc li f . scl = 0 b e fo re brg ti me ou t, b u s co llisi on oc cu r s . s e t b c l i f . inte rrup t c l ea red by so f t w a r e ? 0 ? ? 0 ? ? 0 ? sda scl sen se t s less than tbrg t brg sda = 0 , scl = 1 bcl i f s sspif s set sspif ? 0 ? sda pulled l o w by ot h e r m a st er . reset b r g and ass e rt sda x . s c lx pu ll e d l o w a f t e r b r g ti me o u t set sen , en abl e s t ar t se que nc e i f sd a = 1 , scl = 1 sdax = 0 , s c l = 1 , s e t ssp if inte rrupt s c l e a re d by so f t w a re http:///
? 2014 microchip technology inc. ds20005281a-page 185 mcp191 14/5 28. 5.13 .2 bu s c o ll is i on du r i ng a re pea ted s t a r t cond iti o n d u ring a r e pea ted s t ar t c o n d it ion , a bus c o l l i s io n oc cu r s i f : a ) a l o w le v e l i s s a m p le d o n sda whe n scl goe s fro m low l e v e l to h i gh le ve l b ) sc l go es l o w befo r e sd a i s as se rted l o w , i ndi ca ting th at a not her ma ste r is at tem pti ng to tra n s m i t a dat a ? 1 ? w hen the us er re lea s e s s d a and the pi n i s a llo w ed to fl oat hig h , t he br g is lo ade d w i t h ssp ad d and co unt s d o w n to ze ro. the sc l pi n is th en de as sert ed an d, w h en s a m p l ed hig h , t he sd a pin is s a mp le d. if sd a is low , a bu s co llision has occu r r ed ( i .e., another ma ster is attemptin g t o trans mit a dat a ? 0 ?, figure 28-28 ). if sd a is sampl ed high, the br g is relo aded and beg ins co unting. if sd a g oes f r om high t o low before t h e br g tim e s out, no bus c o llisio n o ccurs bec ause no tw o ma sters can a ssert sd a at exa c tly the s ame time . if sc l g oes from hig h to l o w bef ore th e br g t i me s o u t an d sd a h a s n o t al read y be en as se rted , a bus c o l lisio n oc c u rs . in t h is c a s e , an oth e r mas t e r i s atte mp tin g to t r an sm it a da ta ? 1 ? du ring th e r epe ate d s t art co ndi t io n (re fer t o figure 28-29 ). if, a t t he en d of the br g tim e ou t, both sc l a nd sd a ar e s t il l hig h , the sd a p i n is dri v e n l o w a n d the br g i s re loa ded and be gin s c oun tin g . at the e n d of th e c o un t, re gard l es s of the s t at us of the sc l pi n, the sc l pin i s d r i v en l o w a n d t h e r e p e a t e d s t a r t co nd i t io n is c o m p le te. figure 28-28 : bus collision d u ring a r e p e ate d s t art conditi o n ( c a s e 1) figure 28-29 : bus collision d uring a r e p e ate d s t art conditi o n ( c a s e 2) sda scl rsen bclif s sspif c l ea red by software ? 0 ? ? 0 ? sampl e sd a w h en sc l go es hig h . if sda = 0 , s e t bc lif and rel e as e sd a and sc l. sda scl bclif rsen s sspif t br g t br g ? 0 ? scl go es low be fo re sda, s e t bc lif . re l eas e sd a and sc l. inte rrup t c l ea red by so f t w a re ? 0 ? http:///
MCP19114/5 ds20005281a-page 186 ? 2014 microchip technology inc. 28. 5.13 .3 bu s c o ll is i on du r i ng a s t op c o n d it ion bu s c o l lisio n o c c u rs du ring a s t o p c ond iti on if: a ) af t e r t he sd a p i n has b een d eas se rted an d a llo w ed to fl oat h i gh , sd a i s s a m p le d low af ter th e br g h a s tim ed out . b ) af t e r the sc l pi n i s de ass e rt ed, sc l is s a m p le d l o w be fore sd a go es hi gh. th e s t op co ndi tio n beg in s w i th sd a as se rted lo w . wh en sd a is s a m p le d low , th e sc l pin i s al low e d to f lo a t . w h en t h e p i n i s sa mp le d hi g h ( c lo c k a r bi t r at i o n) , th e bau d r a te g e n e rat o r is l oad ed w i t h ssp ad d an d co u n ts do w n to 0 . a fte r t h e b r g t i m e s ou t , s d a is s a m p le d. if sd a is sa mp le d l o w , a b u s co lli si on ha s oc c u rred . thi s is due to an othe r ma ste r a tte mp ting to dr ive a dat a ? 0 ? ( figure 28-30 ). if th e sc l pi n is s a m p le d l o w be fore sd a is allo w e d t o float hig h , a bu s c o l lis io n oc c u rs . thi s i s a not her c a s e o f an othe r m a st er at tem p ti ng to d r iv e a dat a ? 0 ? ( f i g u re 2 8 -3 1 ). figure 28-30 : bus collision d uri ng a st op condition (cas e 1) figure 28-31 : bus collision d uri ng a st op condition (cas e 2) sda scl bclif pen p sspif t br g t br g t br g sda a s s e rted low ? 0 ? ? 0 ? sda sa m p led low af te r t br g , se t b c lif sda scl bclif pen p sspif t br g t br g t br g assert sda ? 0 ? ? 0 ? scl g o e s l o w be fore sd a go es hi gh, se t b c li f http:///
? 2014 microchip technology inc. ds20005281a-page 187 mcp191 14/5 t able 2 8 -2: s um mar y of re giste r s ass o ciated wi t h i 2 c op eration na me bit 7 b i t 6 b it 5 b i t 4 b it 3 b it 2 b it 1 b it 0 re s e t va l u e s on pa ge: int c on gie peie t0ie inte ioce t0if intf io cf 93 pie1 ? adie bclie sspie cc2ie cc1ie tmr2ie tm r1ie 94 pir1 ? adif bclif sspif cc2if cc1if tmr2if tm r1if 96 tri s g p a trisa7 trisa6 trisa5 ? trisa3 trisa2 trisa1 trisa0 111 trisgpb trisb7 trisb6 trisb5 trisb4 ? ? t r isb1 trisb0 11 6 ssp add a dd7 add6 add5 add4 add3 a d d2 add1 add 0 193 sspbuf s y n c h ro nou s se ria l po rt rec e i v e buf f er/t ra ns m i t reg i s t er 15 3 * sspcon1 w co l sspov sspen ckp sspm 3 sspm 2 sspm 1 sspm 0 190 sspcon2 g cen a c k st a t a c kdt a cken rcen pen rsen sen 191 sspcon3 a c k t i m p cie s cie b oen s daht sbcde ahen dhen 192 sspm sk1 m sk7 m sk6 m sk5 m sk4 m sk3 m sk2 m sk1 m sk0 193 sspst a t sm p c ke d/a psr/w ua bf 189 sspm sk2 m sk2 7 m sk26 m sk25 m sk24 m sk2 3 m sk22 m sk21 m sk2 0 194 ssp add2 add2 7 a dd2 6 a dd2 5 a dd2 4 a dd2 3 a dd2 2 a dd2 1 a dd2 0 194 le gen d : ? = un im ple m e n te d, re ad as ? 0 ?. sha ded c e lls a r e no t u s ed by th e m ssp m odu le in i 2 c mo de. * page provides register information. http:///
MCP19114/5 ds20005281a-page 188 ? 2014 microchip technology inc. 28. 6 b aud rate genera tor t h e m s sp mo du l e ha s a b a u d r a t e ge ne r a t o r a v ai la ble for c l oc k g ene rati on i n the i 2 c ma st e r mo de . th e ba ud r a te ge nerat or (br g ) relo ad val u e is pl ace d in t h e s s p a d d r e gi st e r . w h en a w r i t e o c c u r s t o sspbuf , th e ba ud rate gene rato r wil l a u tom a t i c a ll y b egi n c oun tin g d o w n . o nc e t he g i v en ope rati on is co mp lete , th e i nter nal cl oc k w i ll a u to ma tic a ll y sto p c oun tin g an d t he c l o c k pi n w i l l re ma in in i t s las t s t a t e. an in terna l s i g nal ?r el oad ? in figure 28-32 triggers th e v a lu e fro m ssp add to b e lo ade d in to th e brg cou n te r . th is oc c urs tw ic e for eac h os ci lla tio n o f t he mo dul e c l oc k l i ne . the log i c dic t at ing when t he re loa d si gn al i s as s e rte d dep en ds o n the m o de th e m ssp i s b e in g op era t ed in. t abl e 2 8-3 de mo ns trate s cl oc k rate s ba sed o n i n st ruct ion c y c l es an d t he br g v a l ue l o a ded in to ssp add. eq ua t i o n 2 8 - 1 : figure 28-32 : baud rate ge ner a to r block diagram f clock f osc sspadd 1 + ?? 4 ?? -- --- -- -- -- -- -- -- -- --- -- -- -- -- -- -- -- --- -- -- --- = note: values of 0x00, 0 x 0 1 and 0 x 0 2 are n o t v a li d fo r s s p a d d w hen us ed as a bau d rat e gen e ra tor f o r i 2 c . t h i s i s a n i m p l em en t ati on lim it atio n. t a ble 2 8 -3: m s s p clock ra t e w / brg f os c f cy brg v a l u e f cl o ck ( 2 roll ov e r s of brg) 8m h z 2m h z 0 4 h 4 0 0 k h z ( 1 ) 8m h z 2m h z 0 b h 1 6 6 k h z 8m h z 2m h z 1 3 h 1 0 0 k h z note 1 : th e i 2 c i n te rfac e d oes no t c onf orm to the 400 kh z i 2 c s pecifi c a t io n (w hi ch ap pli e s to r a tes g r eate r th an 1 0 0 k h z ) in all de t a i l s , bu t m a y be use d wi th c a re wher e hi ghe r ra tes are requ ire d b y th e a ppl ic ati on. sspm<3:0> brg down co u n te r sspclk f osc /2 sspadd<7:0> sspm <3:0> scl re l o a d co n t r o l reload http:///
? 2014 microchip technology inc. ds20005281a-page 189 mcp191 14/5 r e gi ste r 2 8 - 1 : ssp st a t : ss p s t a t u s r e gi ste r r/w - 0 r / w -0 r-0 r -0 r-0 r -0 r-0 r -0 smp cke d/a psr/w ua bf bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 sm p : da t a inpu t sa mpl e b i t 1 = s lew ra te con t rol di sa ble d fo r s t and ard sp eed m ode (10 0 kh z a nd 1 m h z ) 0 = s lew ra te con t rol en abl ed for h i gh s pee d m ode (40 0 k h z) bi t 6 ck e : c l oc k edge sel e c t bi t 1 = e nab le inp u t l ogi c so tha t thre sh old s are c o m p l i an t w i t h sm bu s s p e c i f ic ati o n 0 = d i s a b le sm bu s s p e c if ic inp u t s bit 5 d/a : data/address bi t 1 = i ndi ca tes tha t th e l a s t by te rece iv ed or tr ans mi tted was da t a 0 = i nd i c a t e s t h at t h e l as t b y te r ec ei v ed or t r an s m i t t e d w a s a d dr e ss bit 4 p: s t op bit (thi s b i t i s c l e a re d whe n th e m ssp m o d u le is di s a ble d , sspe n is c l eare d .) 1 = i ndi ca tes tha t a s t op b i t has be en dete c t ed l a s t (th i s bi t is ? 0 ? on rese t) 0 = s to p b i t wa s n o t d e te cte d l a s t bi t 3 s: s t art b i t (thi s b i t i s c l e a re d whe n th e m ssp m o d u le is di s a ble d , sspe n is c l eare d .) 1 = i ndi ca tes tha t a s t art b i t h a s be en dete c te d l a s t (th i s bit is ? 0 ? on rese t) 0 = s t a rt b i t wa s n o t d e te cte d l a st bi t 2 r/ w : r ead/write b i t info rma t io n t h i s bi t ho lds the r/w bi t i n for m a t ion fol l o w ing the la st a d d r es s m a tc h. thi s b i t i s onl y v a l i d from the add res s m a tc h to the next start bit, stop bit, or not ack bit. in i 2 c s l ave mo d e : 1 =r e a d 0 = write in i 2 c m a ste r mo de: 1 = t rans mi t i s i n p r ogre s s 0 = t rans mi t i s n o t i n p r ogre s s o r -i ng t h is bi t with sen, rsen, pen, rcen or acken wil l i n di c a te i f the m ssp is in idl e m o de . bi t 1 ua : u pda te ad dres s bit (10 - bit i 2 c mo de onl y) 1 = i ndi ca tes tha t th e u s e r nee ds to upd ate the ad dres s in the ssp ad d re gis t e r 0 = a ddre s s do es not ne ed t o b e up dat ed bi t 0 bf : buf f er ful l s t atu s bit re ce i v e : 1 = r e c e i v e c o m p le te, sspbuf i s fu ll 0 = r e c e i v e n o t c o m p le te, sspbuf i s e m p t y t r ans mi t: 1 = d a t a tran s m it i n p r ogre s s (d oes no t in c l ude the ack a nd s to p b i t s ), sspbuf is ful l 0 = d a t a tran s m it c o m p l e te (doe s not inc l u de the ack an d s t op bit s ), sspbuf i s e m p t y http:///
MCP19114/5 ds20005281a-page 190 ? 2014 microchip technology inc. regis t er 28-2: s s p c o n 1 : ss p co n t ro l regis t er 1 r/c/hs-0 r/c/hs-0 r/w -0 r / w -0 r/w -0 r /w -0 r/w -0 r /w -0 wcol sspov sspen ckp sspm <3:0 > bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red h s = bit is se t by ha rdware c = us er c l e a red bi t 7 wco l : w r ite c o ll is ion d e te ct bit ma ste r mo de : 1 = a writ e to the sspbuf reg i s ter was a ttem p t ed whi l e the i 2 c co ndi tio n s w e r e n o t va lid f o r a trans m i s s io n t o be s t arte d 0 = n o c o ll is ion slav e m o d e : 1 = t he sspbuf reg i s t er is writt en whil e it is s t il l t r ans m i tti ng the p r ev iou s word (m u s t be c l e a red in sof t w a r e ) 0 = n o c o ll is ion bi t 6 sspo v : r e c e iv e o v erfl ow in dic a to r bi t ( 1 ) 1 = a by te is re c e iv ed whi l e the sspbuf reg i s t er is s t il l hol din g the pre v i ous b y te . sspo v is a ?d on? t c a re ? in t r an s m it m o de (m u s t b e c l e a red in s o f tware ). 0 = n o ov erfl ow bi t 5 sspen: syn c h r ono us seri al port e nab le bit in b o th mo des , w h en e n a b le d, th es e p i ns m u s t be pro perl y con f ig ured as in pu t or o u tp ut 1 = e nab les th e s e ri al por t an d c o n f ig ures th e sd a and sc l pin s as the so urc e o f th e s e ri al po rt pi ns ( 2 ) 0 = d i s a b le s ser i al po rt an d c onf igu r es the s e pi ns as i/o po rt pi ns bi t 4 ck p : cloc k pola rity sel e c t bi t in i 2 c s lave m o d e : sc l rel e a s e co ntrol 1 = e nab le clo c k 0 = h o l d s clock low (clock stretch). (used to ensure data setup time.) in i 2 c m ast e r mo de: u n us ed in this m ode bi t 3- 0 sspm < 3 :0> : sy n c h r ono us seri al port m o d e se lec t b i t s 0000 = re se rve d 0001 = re se rve d 0010 = re se rve d 0011 = re se rve d 0100 = re se rve d 0101 = re se rve d 0110 = i 2 c sl av e m o d e , 7 - bit add res s 0111 = i 2 c sl av e m o d e , 1 0 -bi t ad dre s s 1000 = i 2 c m a s t er mo de, cl oc k = f os c /(4 * (ssp add+1)) ( 3 ) 1001 = re se rve d 1010 = re se rve d 1011 = i 2 c f i rm ware-co n tro lle d m a s t er m o de (s lav e i d le ) 1100 = re se rve d 1101 = re se rve d 1110 = i 2 c sl av e m o d e , 7 - bit add res s w i th s t a r t a nd s t o p bi t i n ter r upt s e nab led 1111 = i 2 c sl av e m o d e , 1 0 -bi t ad dre s s w i th s t art and s t op b i t inte rrup t s ena ble d note 1 : in m a st er m o d e , th e o v e r flo w bit is no t se t s i nc e each n e w re cep t io n (a nd tran sm is si on) i s ini t ia ted by wri t ing to the sspbuf re gis t e r . 2: w hen ena bl ed, the sd a an d sc l pin s m u s t b e c onf igu r ed as in put s . 3: ssp ad d v a lu es of 0 , 1 or 2 are not su ppo rted for i 2 c mo de. http:///
? 2014 microchip technology inc. ds20005281a-page 191 mcp191 14/5 regis t er 28-3: s s p co n 2 : ss p contro l regis t er 2 r/w - 0/0 r -0/0 r/w - 0 / 0 r / s /hs-0/0 r /s/ h s-0/0 r /s/hs-0 / 0 r /s/hs-0 / 0 r / w /hs-0 / 0 g c en ackst a t ackdt a cken rcen pen rsen sen bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n /n = v a lue at por and bo r / v a lue at all oth e r r e se t s ? 1 ? = bit is se t ? 0? = bi t is c l ea red h = bit i s se t by ha rdware s = us er s e t bi t 7 gc e n : g e n e ra l c a l l en abl e b i t ( i n i 2 c sl av e m o d e on ly ) 1 = e nab le inte rrup t whe n a gen era l c a ll ad dres s (0x 00 or 00 h) i s rec e iv ed in the sspsr reg i s t er 0 = g e nera l c a l l ad dre s s di sa ble d bi t 6 a ckst a t : ac k now l edg e s t at us bit (in i 2 c mo de onl y) 1 = a ck now l edg e w a s n o t re ce iv ed 0 = a ck now l edg e w a s re ce iv ed bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: v a l u e tran sm itt ed w h en the us er i n iti a te s a n ac k now l edg e s equ enc e at th e e nd of a rec e i v e 1 = n o t ac kn ow le dge 0 = a ck no w l ed ge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = i nit i at e ac kno w led ge seq u e n ce on sd a and sc l pi ns and tran sm it ac kd t dat a bi t. au tom a ti ca lly c l e a re d by h a rdwa re. 0 = a ck now l edg e s e q uen ce idl e bi t 3 rc e n : r e ce iv e en abl e b i t (i n i 2 c m a s t er mo de o n l y ) 1 = e nab les r e c e i v e mo de for i 2 c 0 = r ec ei ve id l e bit 2 pen: stop condition enable bit (in i 2 c master mode only) sck release control: 1 = i nit i at e s t op co ndi tio n o n sd a a nd sc l pi ns . aut o m a tic a l l y cl ear ed b y hard w a re. 0 = s to p c ond iti on idl e bi t 1 rs e n: r epe ate d s t art c ond iti on enab led bi t (in i 2 c ma s t e r mo de o n l y ) 1 = i nit i at e r e p eat ed s t a r t c ond iti on on sd a and sc l p i ns . au tom a ti ca lly c l ea red by ha rdw a re . 0 = r ep ea t e d s t a r t c o nd it i o n i dl e bi t 0 sen: s t art c o ndi tio n en abl ed bit (in i 2 c ma ste r m ode onl y) in m a s t er mod e : 1 = i nit i at e s t art co ndi tio n on sd a a nd sc l pi ns . aut o ma tic a l l y cl eare d b y h a rd w a re. 0 = start condition idle in slave mode: 1 = c l o c k s t re tch i ng is en abl ed for both sla v e t r an sm it a n d slav e r e ce iv e (s tret ch ena ble d ) 0 = c l o c k s t re tch i ng is di sa ble d note 1 : fo r bi t s acken, rcen, pen, rsen, sen: if the i 2 c mo du le i s not in t he idle m ode , th is bit ma y n ot be s et (no s p o o li ng) and th e sspbuf m a y n o t b e wri tten (or wri tes to the sspbuf a r e d i s abl ed). http:///
MCP19114/5 ds20005281a-page 192 ? 2014 microchip technology inc. regis t er 28-4: s s p co n 3 : ss p co n t ro l regis t er 3 r-0/0 r /w - 0 /0 r/w - 0 / 0 r /w -0 /0 r / w - 0 / 0 r /w -0/ 0 r/w - 0 / 0 r / w -0 /0 acktim p c i e scie boen sdaht sbcde ahen dhen bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n /n = v a lue at por and bo r / v a lue at all oth e r r e se t s ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7 a ckt im : ack now l edg e t i me st atu s b i t (i 2 c mo de on l y ) ( 2 ) 1 = i ndi ca tes the i 2 c bu s i s in a n ac k now l edg e s equ enc e, se t on 8 th f a ll ing ed ge of sc l cl oc k 0 = n o t a n ac kn ow le dge se que nc e, c l e a red on 9 th r i si ng edge o f sc l clo c k bi t 6 pcie : s t op cond iti on inte rrupt ena b le bi t (i 2 c m ode on ly) 1 = e nab le inte rrup t on de tect io n of s t op con d i t ion 0 = s top det ec tion in terru pt s are di sa ble d ( 1 ) bi t 5 scie : s t art cond iti on inte rrupt ena b le bi t (i 2 c m ode onl y) 1 = e nab le inte rrup t on de tect io n of s t art o r re s t ar t co nd itio ns 0 = s t a r t de tect io n in terru pt s a r e disa ble d ( 1 ) bi t 4 bo e n : b u ff er ov er w r i t e e n ab l e b i t in i 2 c master mode: this bit is ignored. in i 2 c slave mode: 1 = sspbuf is updated and ack is ge nera t ed for a rec e i v ed ad dres s/ dat a by te , ig nori ng the st a t e o f the sspo v bit onl y if th e bf bi t = 0 . 0 = sspbuf i s on ly up dat ed wh en sspo v is c l ear . bi t 3 sda h t : sda ho ld t i m e sel e c t io n b i t 1 = m i n im um of 300 ns ho ld tim e o n sd a a f te r the fal l i ng e dge of sc l 0 = m i n im um of 100 ns ho ld tim e o n sd a a f te r the fal l i ng e dge of sc l bi t 2 sbc d e: slav e m o d e bu s c o lli si on d e tec t en ab le b i t (i 2 c slav e m o d e o n ly ) if, on th e ris i ng e dge o f scl, sda is s a m p le d low whe n the m o d u le o u tp ut s a h i gh s t a t e, th e bclif bi t in t he pir 1 re gis t er is se t an d b u s goe s idl e . 1 = e nab le sla v e bu s c o l lis io n i n ter r upt s 0 = s lav e b us co lli si on inte rrup t s are dis ab l ed bi t 1 ah e n : addre s s h o l d en abl e b i t (i 2 c sl av e m o d e on ly ) 1 = f oll ow i ng t he 8 th fa ll ing ed ge of sc l for a m a tc hi ng rec e iv ed ad dres s by te; c kp bi t in the sspco n 1 reg i s t er wi ll b e c l e a red an d th e scl will be he ld l o w . 0 = a d d r es s h o l d in g i s d is a bl ed bi t 0 dh e n : d a ta h o l d e n ab l e b i t ( i 2 c sla v e mo de onl y) 1 = f oll ow i ng t he 8 th fa lli ng edg e o f sc l for a re cei v e d d a t a by te; sl av e ha rdw a r e c l ea rs the c kp bi t in t he sspco n 1 reg i s t er a nd s c l is he ld low . 0 = d a t a hol din g i s d i s abl ed note 1 : th is bi t ha s n o e f fe ct in slav e m od es w her e s t art and s t op co ndi tio n de tec t io n i s e x p lic it ly lis ted as e nab led . 2: th e ackt im st a t us bi t is on ly ac tiv e wh en the ahen bi t or d h en bit is se t. http:///
? 2014 microchip technology inc. ds20005281a-page 193 mcp191 14/5 reg i s t er 28- 5: ss pm sk 1: ss p mas k re gi st e r 1 r/w - 1 r / w -1 r/w - 1 r / w -1 r/w - 1 r /w -1 r/w - 1 r /w -1 m sk<7:0 > bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 1 ms k < 7 : 1>: ma sk bi t s 1 = t he rec e iv ed ad dres s bit n i s c o m p a r ed to ssp ad d < n> to dete c t i 2 c add res s m a t c h 0 = t he rec e iv ed ad dres s bit n i s n o t u s e d to de tec t i 2 c ad dres s ma tch bi t 0 ms k < 0 > : m a s k b i t for i 2 c sl av e m ode , 1 0 -bi t add r es s i 2 c slav e m o d e , 1 0 -b it a ddre s s (sspm <3: 0 > = 0111 or 1111 ): 1 = t he rec e iv ed ad dres s bit 0 i s c o m p a r ed to ssp ad d < 0> to dete c t i 2 c add res s m a t c h 0 = t he re cei v e d ad dres s bi t 0 is n o t us ed to d e te ct i 2 c add res s m a tc h i 2 c sl ave mod e , 7-b i t ad dre s s , the bit is ig nore d regis t er 28-6: ss p a d d : ms sp addre ss and baud r a te re gis t e r 1 r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 ad d < 7: 0> bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ent ed b i t, rea d as ?0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red master mode: bi t 7- 0 a d d < 7:0> : b a ud r a te c l oc k d i vi de r bi ts sc l pi n c l o c k pe riod = ((ad d < 7:0> + 1 ) * 4)/ f os c 10-bit slave mode ? most significant address byte: bi t 7- 3 n o t use d : u n us ed f o r m o s t s i g n i f ic an t a d d r e ss b y t e . b i t sta t e o f th i s r e gi st e r is a ? d on ? t c a r e ? . b i t p a tte rn s ent b y m a s t er i s fix e d by i 2 c s pec ifi c a t io n an d mu st b e eq ual to ? 1111 0 ? . ho we v e r , th o s e b i t s a r e c o m p a r ed by hard w are and are no t af fec t ed by th e v a lu e i n th is reg i s t er . bi t 2- 1 a d d < 2:1> : t w o mo st sign ifi c an t b i t s of 10-b i t a d d r ess . bi t 0 n o t us ed : u n us ed i n t h is m ode . bit st ate is a ?d on? t c a re? . 10-bit slave mode ? least significant address byte: bi t 7- 0 a d d < 7:0> : eig h t l eas t si gni fic a n t bi t s of 1 0 -bi t a ddre s s 7-bit slave mode: bi t 7- 1 a d d < 7:1> : 7-b i t a ddre s s bit 0 not used: unused in this mode. bit state is a ?don?t care?. http:///
MCP19114/5 ds2000 5281a-page 194 ? 2014 mic r ochip t e c hnology i n c. reg i s t er 28- 7: ss pm sk 2: ss p mas k re gi st e r 2 r/w - 1 r / w -1 r/w - 1 r / w -1 r/w - 1 r /w -1 r/w - 1 r /w -1 ms k 2 <7: 0 > bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 7- 1 m s k 2 <7 : 1 >: ma sk bi ts 1 = t he rec e iv ed ad dres s bit n i s c o m p a r ed to ssp ad d 2 to de tec t i 2 c ad dre s s ma tc h 0 = t he rec e iv ed ad dres s bit n i s n o t u s e d to de tec t i 2 c ad dres s ma tch bi t 0 ms k 2 < 0 >: ma sk bi t for i 2 c slav e mod e , 10-b i t ad dre s s i 2 c slav e m o d e , 1 0 -b it a ddre s s (sspm <3: 0 > = 0111 or 1111 ): 1 = t he rec e iv ed ad dres s bit 0 i s c o m p a r ed to ssp ad d 2 <0 > to de tec t i 2 c ad dre s s ma tc h 0 = t he re cei v e d ad dres s bi t 0 is n o t us ed to d e te ct i 2 c add res s m a tc h i 2 c sl ave mod e , 7-b i t ad dre s s , the bit is ig nore d reg i s t er 28- 8: ss p a d d 2: ms sp add res s 2 r/w - 0 r / w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 add2 <7 :0 > bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? u = bi t is un ch ang ed x = bit is unk no w n -n = v a l ue a t po r ? 1 ? = bit is se t ? 0? = bi t is c l ea red ma st e r m o d e : bi t 7- 0 a dd2 <7:0 >: ba ud r a te c l oc k d i vi der bit s sc l pi n c l o c k pe riod = ((ad d < 7:0> + 1 ) * 4)/ f os c 1 0 -bit sl ave mode ? most significant address byte: bi t 7- 3 n o t use d : u n us ed f o r m o s t s i g n i f ic an t a d d r e ss b y t e . b i t sta t e o f th i s r e gi st e r is a ? d on ? t c a r e ? . b i t p att ern s ent by ma ste r i s fix ed b y i 2 c s pe c if ic atio n and m us t be eq ua l to ? 11110 ?. h ow e ve r , t h os e bi ts are c o m p a r ed by ha rdw a re an d are no t af fec t e d by th e v a l ue i n t h is reg i s t er . bi t 2- 1 a dd2 <2:1 >: t w o m o s t sig n if ica n t bit s o f 10 -bit ad dres s bi t 0 n o t us ed : u n us ed i n t h is m ode . bit st ate is a ?d on? t c a re? . 1 0 -b it sl ave mod e ? leas t sig n ific ant a d dr ess byt e : bi t 7- 0 a dd2 <7:0 >: ei ght lea st sign ifi c a n t b i t s of 10-b i t add res s 7- b i t s l av e mode: bi t 7- 1 a dd2 <7:1 >: 7 - bit add res s bi t 0 n o t us ed : unused in this mode. bit state is a ?don?t care?. http:///
? 2014 microchip technology inc. ds20005281a-page 195 mcp191 14/5 2 9 .0 ins t r uction s e t s u m m ary th e mc p1 91 14 /5 ins t ru cti on s e t is hi gh ly ort hog ona l a nd i s com pr i se d o f th ree bas ic ca teg orie s : ? byt e -orie n ted ope rati ons ? bit-o riente d o pera t io ns ? li teral and cont r o l op erat ion s ea ch i n s t ruct io n is a 14 -bit w o rd di vid e d i n to a n op cod e , w h ic h s pe c i f ies t he ins t ruc t i on typ e, and on e or m or e ope rands , wh ic h fu rthe r sp ec ify the o per atio n o f th e i n s t ruc t io n. the form at s f o r e a c h o f th e c a te gori e s is p r es ent ed i n fig u re 29- 1 , whi l e th e v ari ous op co de fiel ds are su mm ari z e d i n t abl e 2 9-1 . t able 29-2 l i st s the instru ctio ns re cogn ize d by the m p asm tm as sem b ler . fo r by te-ori ente d in st ruc t ion s , ?f ? repr ese nt s a fil e re gist er de sig n a t or a nd ?d? re pres en t s a d e s t in atio n d esi gn ator . the file regi st er de si gna tor s pec ifi es w hic h fi le regi st er i s to be us ed by the in structi on. th e de sti nat ion d e s i gn ato r s p e c i f ies w here t he res u l t of th e op era t io n is to b e pl ac ed. if ?d ? is z e ro, t he re su lt i s p l ac ed in the w re gist e r . if ?d? is on e, the resu lt is pl ace d i n th e fi le regi st er s pec ifi e d in the ins t ru cti on. fo r bit-orie n ted ins t ruc t i ons , ? b ? repre s e n t s a bi t fiel d d esi gn ator , w hic h s ele ct s th e bi t af fec t ed b y th e o perat io n, w h ile ?f ? re pre s e n t s the add res s o f th e file in wh ich the bi t is l o ca ted . for liter al and co ntr ol oper ations, ? k ? represents an 8-bit or 1 1 -bit const ant, or liter al value. o n e in str u ct ion c y c l e co ns ist s of f our os ci lla tor peri ods ; fo r an os cil l a t or fre q u enc y o f 4 m h z , thi s g i v e s a no rma l i n s t ruc t io n e x e c ut ion ti me of 1 s . all ins t ru cti ons a r e e x ec ut ed w i th in a si ngl e ins t ruc t i on cy cl e, unl es s a c ond iti ona l tes t i s tru e , or t he pro g ram cou n te r i s c han ge d as a res ul t of an in str uct ion . w hen t his occ urs , th e ex ec uti on t ak es t w o in stru cti on c y c le s, w i th th e s ec ond cy c l e e x e c u t ed as an nop . a l l i n s t r u ct i o n e x a m p l es us e t h e f o r m a t ? 0xhh ? t o re pres en t a h ex ade ci ma l num be r , w here ? h ? si gni fie s a h e xa de cim a l di git . 29. 1 r ead- m odif y -w ri te o p erat ions an y ins t ru cti on tha t s p e c i f ies a fi le reg i s t er as p a rt of th e ins t ruc t i on per form s a r ead -mo d if y-w r ite (r m w ) o pera t io n. th e reg i s t er is rea d , th e da t a i s m odi fie d , a nd t he re su lt i s s t o r ed a c c o rd ing to e i th er th e i n s t ruc t io n or th e de sti nat ion des ig nat or ?d ?. a rea d op e r at i o n is pe r f or m e d on a r e gi st e r e v en if t h e i n s t ruc t io n w r it es to t hat regi st er . fo r ex am ple , a clr f porta in st r u ct i o n wi ll r e ad po r t gp a, c l ea r al l th e da t a b i t s , th en w r i t e t he re su lt ba c k to p o r t g p a . th i s ex am pl e w o u l d ha ve t he u nin ten ded co ns equ enc e of c l e arin g t he con di t ion th at s e t s th e io cif flag . figure 29-1: gene ral forma t fo r ins t ructions t able 2 9 -1: o pc ode fie l d de scri ptions fiel d d esc r iption f r eg i s t e r f i le a d d r es s ( 0 x0 0 t o 0x 7f ) w w ork i n g re gis t er (ac c u m u l ato r ) b b i t ad dre s s wi th in an 8-bi t fi le r egi ste r k l ite r al fiel d, con s t a nt dat a o r lab e l x d o n ?t ca re l o ca tio n (= 0 or 1 ). t he a s s e m b l e r wi ll g e n e rate c ode with x = 0 . i t is th e rec o m m end ed form of us e fo r co mpat i b i l i t y w i t h a l l m i c r oc hi p s o ft w a r e t o ol s. d d e s ti nat ion se le ct; d = 0 : st o r e r e su l t i n w , d= 1 : sto r e re su lt i n f ile reg i s t er f. de fau l t i s d = 1. pc pro g ra m c o unt er to t i me -out bi t c c a rry b i t dc di g i t c a rry b i t z z ero bit pd power-down bit b y t e - o r i e nt e d f i le r e gi s t e r op e r a t i ons 1 3 8 7 6 0 d = 0 f o r dest i nat ion w op code d f ( f il e # ) d = 1 for destination f f = 7 - bit f ile re gi s t er addres s bi t-o ri en te d fi l e r e g i ster o p e rati o n s 1 3 1 0 9 7 6 0 op c o d e b ( b it # ) f ( f il e # ) b = 3-bit bit addres s f = 7 - bit f ile re gi s t er addres s lit e r a l a n d c o n t r o l ope r a t i ons 1 3 8 7 0 op c o d e k ( l i t e r a l ) k = 8-bit immediate value 13 1 1 1 0 0 opcode k ( l ite r a l ) k = 11-bit immediate value general call and goto in st ruct i o n s onl y http:///
MCP19114/5 ds20005281a-page 196 ? 2014 microchip technology inc. t a ble 2 9 -2: m cp 191 1 4 /5 i n struc t i o n se t mn em o n i c , op er and s d e scr ip tion c ycl es 14 -bit o p co de st at u s affec t ed no te s ms b l s b byte-orient e d file r e g i st er opera t ions addwf andwf cl r f cl r w com f decf decfsz incf incfs z io r w f mov f mov w f nop rl f rrf subw f sw apf xor w f f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d a dd w an d f a n d w wi t h f cl e a r f cl e a r w co m p l e me n t f d ec r em en t f de cre m e n t f, sk ip i f 0 i n c r em ent f i n c r em ent f, sk ip if 0 i n c l us iv e o r w w i th f mo ve f m o v e w to f n o o perat io n ro t a t e le f t f thro ugh carry ro t a t e rig h t f thro ugh carry s ubtra ct w fro m f sw ap ni b b l e s in f e x c l us iv e o r w w i th f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z z z z c c c, dc, z z 1 , 2 1 , 2 2 1 , 2 1 , 2 1 , 2 , 3 1 , 2 1 , 2 , 3 1 , 2 1 , 2 1 , 2 1 , 2 1 , 2 1 , 2 1 , 2 bit - oriented f i le register opera t ions bcf bsf bt fsc bt fss f, b f, b f, b f, b b i t c l ear f b i t se t f b i t t e s t f, ski p if cle a r b i t t e s t f, ski p if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1 , 2 1 , 2 3 3 li teral and contro l opera t i o ns addl w andl w cal l cl r w dt got o io rl w mov l w retf ie retl w return sl eep subl w xorl w k k k ? k k k ? k ? ? k k a dd l i te ral and w a n d l i t e r a l wi th w c a ll subr outi n e c l ea r w a tc hd og t i me r g o to a d d r es s i n c l us iv e o r l i tera l wi th w m o v e lite r al to w re turn fro m i n te rrupt re turn with li tera l i n w re turn fro m su brou tin e g o int o s t an dby m o d e s ubtra ct w fro m lit eral e x c l us iv e o r l i ter a l wi th w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c, dc, z z to , pd z to , pd c, dc, z z note 1 : w hen an i/ o reg i s t er is m odi fie d as a fun c ti on of it se lf (e.g ., m ovf porta, 1 ), the v a lu e us ed w ill b e that v alu e p r es ent on the pin s t hem se lv es . fo r ex am ple , if the dat a l atc h i s ? 1 ? fo r a p i n co nfig ure d as i n pu t an d i s d r iv en low b y a n e x te rna l de vi ce , th e da t a w i ll be writte n b a c k wi th a ? 0 ?. 2: if thi s i n s t ruc t io n i s e x e c u t ed on t he tmr 0 reg i s t er (a nd w here ap pli c a b le , d = 1 ), t he pres ca le r w ill be c l ea red if assi g ned to the t i m e r0 mo dul e. 3: if the prog ram coun ter (pc) is m odi fie d , o r a c o n d it io n a l tes t is tru e , t he i n s t ruc t io n re qui res two cy cl es . th e s e c o n d c y c l e is ex ec uted as an nop . http:///
? 2014 microchip technology inc. ds20005281a-page 197 mcp191 14/5 29. 2 i nstr ucti on descri p ti ons addl w a dd lite r a l a nd w sy nt a x : [ lab e l ] addl w k o p e r and s: 0 ? k ? 255 o p e r ati on: (w ) + k ? (w) s t at us af fe ct ed: c , d c , z d e sc ript ion : t he c o n t en t s of th e w reg i s t er a r e ad ded to the ei gh t-bi t l i te ral ? k ? a nd the res u lt is pl ace d i n th e w re gis te r . addwf a d d w a nd f sy nt a x : [ lab e l ] addwf f , d o p e r and s: 0 ? f ? 12 7 d ?? ? 0 , 1 ? ope r ati on: (w ) + (f ) ? (d est i na tio n ) s t at us af fe ct ed: c , d c , z d e sc ript ion : ad d the con t en t s o f t he w re gis t er wi th re gi ste r ?f ?. if ? d ? is ? 0 ? , the re su lt is s t ored i n t he w re gi ste r . i f ? d ? is ? 1 ? , the res u l t is s t ore d b a ck i n re gis t e r ?f ?. andl w and li te ra l w i th w sy nt a x : [ lab e l ] andl w k op er a n d s : 0 ? k ? 255 ope r ati on: (w ) .and. (k ) ? (w ) s t at us af fe ct ed: z d e sc ript ion : t he c o n t en t s of w reg i st er a r e and? ed wi th t he eig h t-b i t l i te ral ?k ?. t h e r e s u lt is pl a c e d i n t h e w re gis t e r . andwf and w with f sy nt a x : [ lab e l ] andwf f , d o p e r and s: 0 ? f ? 12 7 d ?? ? 0 , 1 ? ope r ati on: (w ) .and. (f ) ? (d est i na tio n ) s t at us af fe ct ed: z d e sc ript ion : an d t he w reg i s t er w i th r egi ste r ? f ?. if ?d? is ? 0 ? , the re su lt is s t ore d in t he w reg i s t er . if ? d ? is ? 1 ?, the re su lt i s sto r ed bac k in r egi ste r ?f ? . bcf bit c l e a r f sy nt a x : [ lab e l ] bcf f,b o p e r and s: 0 ? f ? 12 7 0 ? b ? 7 o p e r ati on: 0 ? (f) s t at us af fe cte d : n o n e d e s c r ipti on : b i t ?b ? i n re gis t er ?f ? i s cle a re d. bsf b it se t f sy nt a x : [ lab e l ] bsf f,b o p e r and s: 0 ? f ? 12 7 0 ? b ? 7 o p e r ati on: 1 ? (f) s t at us af fe cte d : n o n e d e s c r ipti on : b i t ?b ? i n re gist er ?f ? i s set . btf s c b it t e st f, skip if clea r sy nt a x : [ l abe l ] btfsc f,b o p e r and s: 0 ? f ? 12 7 0 ? b ? 7 o p e r ati on: s k i p if (f) = 0 s t at us af fe cte d : n on e d e s c r ipti on : if bi t ?b? i n reg i s t er ?f ? is ? 1 ? , t he ne xt in str u ct ion is ex ec ute d . if bi t ?b? i n reg i s t er ?f ? is ? 0 ? , t he ne xt in str u ct ion is di sc ard ed, and an nop is exec ut e d i n st ea d , m a k i n g th is a tw o - cy cl e i n s t ruc t io n. http:///
MCP19114/5 ds20005281a-page 198 ? 2014 microchip technology inc. btf s s b it t e s t f, sk ip if set sy nt a x : [ l abe l ] b tfss f,b o p e r and s: 0 ? f ? 12 7 0 ? b< 7 o p e r ati on: sk ip if (f ) = 1 s t at us af fe ct ed: n one d e sc ript ion : if bi t ?b ? in regi ste r ?f ? i s ? 0 ?, th e ne xt in stru cti on is ex ec uted . if b i t ? b ? is ? 1 ? , the ne xt inst ru cti on is di sc arde d a nd an nop is ex ec uted in ste ad , m aki ng thi s a t w o - cy cl e i n s t r u c t io n. c a l l c a l l s u brou t i n e sy nt a x : [ lab e l ] cal l k o p e r and s: 0 ? k ?? 204 7 o p e r ati on: (pc ) + 1 ? to s , k ? pc<1 0:0 > , (pcl a t h< 4 : 3 > ) ? pc<1 2:1 1 > s t at us af fe ct ed: n o n e de sc ript ion : cal l su bro u tin e . firs t, re turn a ddre s s (pc + 1) i s p u s hed on to th e s t ac k. the el ev en-b i t i m m edi ate ad dres s is lo ade d i n to pc b i t s <1 0:0 > . th e u ppe r bi t s of th e pc are loa ded from pc la th . call is a tw o - cy cl e i n s t ruc t io n. clrf cl e a r f sy nt a x : [ la bel ] clrf f o p e r and s: 0 ? f ? 12 7 o p e r ati on: 0 0h ? (f) 1 ? z s t at us af fe ct ed: z d e sc ript ion : t he con t en t s of re gi ste r ?f ? are c l e a red an d the z bit is se t. clr w cl e a r w sy nt a x : [ la bel ] cl r w o p e r and s: n o ne op er a t io n : 00 h ? (w) 1 ? z s t at us af fe ct ed: z de s c ript ion : w reg i s t er i s c l e a re d. ze ro (z ) bi t is s e t. clrwdt clea r w a tc hd og t i m e r sy nt a x : [ lab e l ] cl r w dt o p e r and s: n o ne o p e r ati on: 0 0h ? wdt 0 ? wdt p r es ca ler , 1 ? to 1 ? pd s t at us af fected: to , pd de scr i p tion: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. bits to and pd in the st a tu s re gis t e r are se t. c o mf c o mpl eme nt f sy nt a x : [ la bel ] co m f f,d o p e r and s: 0 ? f ? 127 d ? [ 0 , 1 ] o p e r ati on: (f ) ? (d es tin a tio n ) s t at us af fe cte d : z d e s c r ipti on : t he co nten t s of regi ste r ?f ? are com pl em ent ed. if ? d? is ? 0 ?, the res u lt is sto r ed in w . i f ?d ? i s ? 1 ?, the res ult is st ored ba ck i n regi ste r ?f ? . decf de c r e m ent f synt a x : [ l abe l ] decf f, d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] o p e r ati on: (f) - 1 ? (d es tin a tio n ) s t at us af fe cte d : z d e s c r ipti on : d ec rement reg i st er ? f ? . if ?d? is ? 0 ?, the res u l t is s t ore d in th e w reg i s t er . if ? d ? i s ? 1 ?, the res u lt is st ored ba ck in reg i st er ? f ? . http:///
? 2014 microchip technology inc. ds20005281a-page 199 mcp191 14/5 decfsz de c r e m e n t f, sk i p if 0 sy nt a x : [ la bel ] d e c f sz f , d o p e r and s: 0 ? f ? 127 d ? [ 0 , 1 ] o p e r ati on: ( f ) - 1 ? (de s ti na tion ); s k i p if re su lt = 0 s t at us af fe ct ed: n o ne d e sc ript ion : t he co nten t s of r egi ste r ?f ? are d ec r em ent ed. if ? d? is ? 0 ?, th e res u lt i s pla c e d in th e w regi ste r . i f ?d ? i s ? 1 ?, the res u lt is pl ac ed b a c k i n regi ste r ?f ? . i f th e re sul t i s ? 1 ?, t he n e x t i n s t ruc t io n i s e x e c u t ed . if t he r e su lt is ? 0 ?, an nop is e x ec ut ed i n s t ea d, m a k i n g i t a tw o-cy c l e in st r u ct i o n . g o t o u n c ond ition a l bran ch sy nt a x : [ la bel ] g o t o k o p e r and s: 0 ? k ? 20 47 o p e r ati on: k ? p c < 10: 0> p c l a t h <4:3 > ? pc < 12: 1 1 > s t at us af fe ct ed: n o ne de s c ri p t i o n : g oto is an un co ndi tio nal bra nch . t he e l e v en -bi t im me dia t e v a l ue i s l o a ded in to pc b i t s <1 0:0 >. th e u p p e r b i t s of pc are loa ded fro m p c l a t h <4:3 >. got o is a two - cycl e i n st r u ct io n . in c f incr e m en t f sy nt a x : [ la bel ] incf f,d o p e r and s: 0 ? f ? 127 d ? [ 0 , 1 ] o p e r ati on: (f) + 1 ? (d es tin a tio n ) s t at us af fe ct ed: z d e sc ript ion : the co nte nt s of regi ste r ?f ? are inc r em en ted . i f ? d ? is ? 0 ?, th e resu lt is pla c ed in t he w r egi ste r . if ? d? i s ? 1 ?, the res ul t is pl ac ed bac k in regi st er ?f ? . incfsz inc r e m e n t f, sk ip i f 0 sy nt a x : [ la be l ] incfsz f,d o p e r and s: 0 ? f ? 127 d ? [ 0 , 1 ] o p e r ati on: (f) + 1 ? ( des tin a ti on), sk ip if res ult = 0 s t at us af fe cte d : n one d e s c r ipti on : t he co nte n t s of regi st er ?f ? are incr em en ted . if ?d? is ? 0 ? , th e re su lt is pl ac ed i n th e w reg i s t er . if ? d ? i s ? 1 ? , the res u l t is p l ac ed bac k in r e gi s t e r ?f ?. if th e re su lt i s ? 1 ?, the nex t ins t ru cti o n is ex ec uted. if the res u lt is ? 0 ?, a n nop is exec ut e d ins t e ad, ma ki ng i t a two - cy cl e ins t ru cti o n. io rl w i nclu sive o r lite r a l w i th w sy nt a x : [ lab e l ] io rl w k o p e r and s: 0 ? k ? 255 o p e r ati on: (w ) .o r . k ? (w) s t at us af fe cte d : z d e s c r ipti on : t he c o n t en t s of t he w reg i s t er a r e o r ?e d wi th th e e i gh t-bi t li tera l ? k ? . t he r e su lt is pla c e d i n the w re gis te r . io r w f i n c lus i ve o r w w i th f sy nt a x : [ lab e l ] io r w f f,d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] ope r ati on: (w ) .or. (f) ? (de s ti nat i on ) s t at us af fe cte d : z des c r ipti on : i n c l u s i v e o r the w r e gi ste r with re gist e r ?f ?. if ? d ? is ? 0 ?, the res u l t is p l ac ed in the w re gis t e r . if ?d? is ? 1 ?, t he resu lt is pla c e d b ack in re gis t e r ?f ?. http:///
MCP19114/5 ds20005281a-page 200 ? 2014 microchip technology inc. mov f mo ve f sy nt a x : [ la bel ] mo vf f,d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] o p e r ati on: (f ) ? (d es t ) s t at us af fe ct ed: z d e sc ript ion : t he con t en t s of re gi ste r ?f ? are m o v e d to a de st ina t io n d epe nd ent upo n th e s t at us of ?d ?. i f d = 0 , th e d e s t in atio n i s w re gi ste r . if d = 1 , th e d e s t ina t io n is f i l e r e gi st e r ?f ? its e l f . d = 1 is us ef u l t o t e st a fi l e re g i s t er si nc e st a t us fl ag z is a f fe cte d . wo r d s : 1 cyc l e s : 1 ex am pl e: mo vf fsr, 0 af ter i n s t ruc t io n w= v a l u e i n f s r re gi s te r z= 1 m o vl w m ove lite r al to w sy nt a x : [ lab e l ] m o vl w k o p e r and s: 0 ? k ? 255 o p e r ati on: k ? (w ) s t at us af fec ted : no n e d e sc ript ion : th e e i gh t-bi t litera l ? k ? is lo ade d i n to w re gis t er . the ?do n ? t c a res ? w i ll as se mb le a s ? 0 ?s. wo r d s : 1 cyc l e s : 1 ex am pl e: movlw 0x5a af t e r in s t ruc t ion w= 0 x 5 a mo v w f m o v e w t o f sy nt a x : [ lab e l ] mo vwf f o p e r and s: 0 ? f ? 12 7 o p e r ati on: (w ) ? (f) s t at us af fe cte d : n o n e d e s c r ipti on : m ov e d a t a from w regi st er to re gis t e r ?f ?. wo r d s : 1 cyc l e s : 1 ex am ple : mov w f option be fore ins t ru cti o n opt i o n = 0 x f f w = 0x 4f af ter i n s t ruc t io n opt i o n = 0 x 4 f w = 0x 4f n o p n o op er atio n sy nt a x : [ lab e l ] no p o p e r and s: n o ne o p e r ati on: n o op erati o n s t at us af fe cte d : n o n e d e s c r ipti on : n o op erati o n . wo r d s : 1 cyc l e s : 1 example: nop http:///
? 2014 microchip technology inc. ds20005281a-page 201 mcp191 14/5 retf ie re turn from int e rrupt sy nt a x : [ la bel ] retfie o p e r and s: n o ne o p e r ati on: t o s ? pc, 1 ? gi e s t at us af fe ct ed: n o ne de sc ript ion : re turn from in terru pt. s t ack i s po pe d an d t o p - of-s t a ck (t o s ) i s loa ded in the pc. in terru pt s a r e e nab le d by s e tti ng gl oba l inter r upt enab le bit , g i e (i ntco n< 7 > ). th i s i s a two - c ycl e in st r u ct i o n . wo r d s : 1 cyc l e s : 2 ex am pl e: re tfie af ter i n te rrupt pc = t os gi e = 1 retl w r e t urn w i th litera l in w sy nt a x : [ la bel ] retl w k o p e r and s: 0 ? k ? 25 5 o p e r ati on: k ? (w ); to s ? pc s t at us af fe ct ed: n o ne d e sc ript ion : t he w reg i s t er i s loa ded w i th t he e i g h t-b i t l i te ral ?k? . th e p r og ram co unt er i s l oad ed from t he t o p - of-s t a c k (th e ret u rn a ddr ess ) . t h is is a tw o-c y c l e in st r u ct i o n . wo r d s : 1 cyc l e s : 2 ex am pl e: table done ca ll table;w conta ins ;table offset ;va lue go to done ? ? ad dwf pc ;w = off set re tlw k1 ;begin t able re tlw k2 ; ? ? ? re tlw kn ;end of table be fore ins t ru cti o n w = 0x 07 af ter i n s t ruc t io n w = v a l ue of k 8 return r e turn fro m sub r outin e sy nt a x : [ la bel ] return o p e r and s: n o ne o p e r ati on: t o s ? pc s t at us af fe cte d : n o n e d e s c r ipti on : r e t urn fr om s ubro u ti ne. th e s t ac k is pope d a nd the t o p-of -s t a ck (t o s ) i s l oad ed int o th e p r ogra m cou n te r . th is is a two-c y c l e i n st r u ct io n . rlf r ot a t e l e f t f through carry sy nt a x : [ l abe l ] rlf f,d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] o p e r ati on: se e de sc rip t io n be lo w s t at us af fe cte d : c d e scr i p t i o n : t he co nt e n t s of r e gi st e r ? f ? ar e ro t a te d on e b i t to the le f t th roug h th e car r y fl ag . if ? d ? is ? 0 ? , th e re sul t i s pla c e d i n t he w re gis t er . if ?d? is ? 1 ? , th e re su lt i s s t or ed ba ck in reg i s t er ? f ?. wo r d s : 1 cyc l e s : 1 ex am ple : rlf reg1,0 be fore ins t ruc t io n reg1 = 1110 0110 c= 0 af t e r in s t ru c t ion reg1 = 1110 0110 w = 1100 1100 c= 1 register f c http:///
MCP19114/5 ds20005281a-page 202 ? 2014 microchip technology inc. rrf ro t a te right f throug h ca rry sy nt a x : [ lab e l ] rr f f, d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] o p e r ati on: se e d e s c ri ptio n b e lo w s t at us af fe ct ed: c d e sc ript ion : t he con t en t s of re gis t e r ?f ? are ro t a t ed o n e bit to t he r i gh t th roug h t he ca rry flag . if ?d? is ? 0 ?, th e re su lt i s pla c e d in th e w regi ste r . i f ?d ? i s ? 1 ?, t he res u lt is pla c e d ba ck in r e g i st er ? f ? . sl eep enter sl eep mod e sy nt a x : [ lab e l ] s leep o p e r and s: n o ne o p e r ati on: 00h ? wdt , 0 ? wd t pres c a le r , 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd , is cleared. time-out status bit, to , is s e t. w a tc hd o g t i me r and it s pr esc a l e r a r e c l e a red . the proc es so r is p u t i n to slee p mo de w i th th e osc i l l at or sto ppe d. subl w s ubtrac t w fro m lit eral sy nt a x : [ la bel ] s ubl w k o p e r and s: 0 ? k ? 25 5 o p e r ati on: k - ( w ) ??? w) s t at us af fe ct ed: c , dc , z d e sc ript ion : the w re gis t er is su btracte d (tw o ? s comp l e m ent me tho d ) fro m the eig h t-b i t l i te ral ?k? . th e re su lt i s pla c ed in the w r egi ste r . regist er f c result conditi on c= 0 w ? k c= 1 w ? k dc = 0 w< 3:0> ? k< 3:0 > dc = 1 w< 3:0> ? k< 3:0 > subwf s ubtra c t w fr o m f sy nt a x : [ la bel ] s u b wf f,d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] o p e r ati on: (f) - ( w ) ??? d es t in atio n) s t at us af fe cte d : c , dc, z d es c r ipti on : s ubt rac t (tw o? s co mp le men t me tho d ) w regi st er from regi ste r ?f ?. if ?d? is ? 0 ?, the re su lt is sto r ed in t he w re gis t er . if ? d ? is ? 1 ?, t h e r e su lt is sto r ed bac k in regi st er ?f ? . sw apf s w a p ni bble s in f sy nt a x : [ lab e l ] sw apf f,d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] o p e r ati on: (f<3 :0> ) ? (de s t i na tio n <7 :4>), (f<7 :4> ) ? (de s t i na tio n <3 :0>) s t at us af fe cte d : n on e d e s c r ipti on : t he up per and lo w e r n i bb les of reg i s t er ? f ? ar e ex c han ged . if ?d? is ? 0 ? , th e re sul t i s p l ac ed in the w reg i s t er . if ? d ? i s ? 1 ?, the res u l t is pl ac ed i n re gist e r ?f ?. xo rl w e xcl usiv e o r lite r al w i th w sy nt a x : [ la bel ] x o r l w k o p e r and s: 0 ? k ? 25 5 o p e r ati on: (w) .xo r . k ?? ? w) s t at us af fe cte d : z d e s c ription : t he co nte n t s of the w re gis t er are xor ? ed w i th the eig h t-b i t l i t e ral ?k ?. the resu lt is pl ace d i n the w re gis t er . c= 0 w ? f c= 1 w ? f dc = 0 w< 3:0> ? f<3 : 0> dc = 1 w< 3:0> ? f<3 : 0> http:///
? 2014 microchip technology inc. ds20005281a-page 203 mcp191 14/5 xo r w f e xc lusi ve or w w i th f sy nt a x : [ l abe l ] x o r wf f,d o p e r and s: 0 ? f ? 12 7 d ? [ 0 , 1 ] ope r ati on: (w) .xo r . (f) ?? ? des tin a ti on) s t at us af fe ct ed: z d e sc ript ion : ex clu s i v e o r the co nten t s of the w re gi ste r with reg i s t er ? f ?. if ?d ? is ? 0 ? , th e re sul t i s s t ore d i n th e w r e gi st e r . i f ?d ? is ? 1 ?, the res u l t is stored back in register ?f?. http:///
MCP19114/5 ds20005281a-page 204 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 205 mcp191 14/5 30 .0 in-circuit s e r i a l pr o g ram ming? ( i c s p ? ) ic s p a llo w s c usto m er s to manu fa ctu r e c i r c uit boa rd s w i th un pr ogr amme d d e vi ces. p r o g r a mmin g c an be don e a f t e r t h e a s s e m b l y pr oc e s s , a l lo w i n g th e de v i ce t o be pr ogr amm ed w i th t he mo st re cen t fir m w a r e or a cu sto m fi rmw ar e. f i ve pi ns ar e nee ded f or i c s p p r og ra mmin g: ? i cspcl k ? i cspda t ? mclr ?v dd ?v ss (a gn d ) in p r ogr am/v erif y m o de, t he pr ogr am m e mory , u s e r id s and the c onfig urat ion w o rds are pr ogr amm e d t h rou g h seria l communi c a tions. th e ic s p d a t pin is a bidir ection al i/o used fo r t r an s f err i ng the seria l da t a a nd the ic spc lk pin i s the clock inpu t. t he devi c e is pla c ed into a p r ogr am/v e r ify mode by holding the ic spd a t a n d ic sp c lk pins low , w h ile r aising t he mc lr pin f r om v il to v ih h . 30. 1 c omm on progr am mi ng i n te rfa ces c o n nec ti on to a t a rg et de vi ce i s ty pi ca lly don e th roug h an ic sp he ade r . a c o m m on ly fou nd c o n nec tor o n d ev el o pm en t t o o l s i s t h e r j - 1 1 i n t h e 6 p 6c ( 6 - p i n , 6- c onn ec tor) c o n f ig urat ion . r e f e r to fig u re 30- 1 . figure 30-1: icd r j -1 1 s t yle connector inte rface an othe r c onn ec tor o f ten fo und in us e w i th th e pi c k it ? pr ogram m e rs is a st and ard 6-pi n h e ad er w i th 0 . 1 i nc h s p ac in g. r e fer t o fi gu re 30 -2 . f i g ure 30- 2: p i c k it ? s t yle conne ctor inte rface 1 2 3 4 5 6 mclr v ss icspcl k v dd ic s p d a t nc pin desc ri ptio n* 1 = mc l r 2 = v dd ta r g e t 3 = v ss (grou nd) 4 = icspda t 5 = ic spc lk 6 = no co n n e c t ta r g e t pc boar d botto m si de 1 2 3 4 5 6 * t he 6-pi n h ead er (0 .10 0 " sp aci ng) ac ce pt s 0.0 25" s qua re p i ns . pin description* 1 = mclr 2 = v dd t a rget 3 = v ss (a gn d ) 4 = icspda t 5 = ic spc lk 6 = n o c o nne ct pin 1 i ndi ca tor http:///
MCP19114/5 ds20005281a-page 206 ? 2014 microchip technology inc. fo r ad dit i on al i n te rfac e re co mm end ati ons , re fer to yo ur s pec if ic d e vi ce p r ogr amm e r m anu al p r ior to pc b de s i g n. it is reco mm en ded tha t is ol atio n d e vi ce s b e us ed to s e p a rate the pro g ra mm ing pi ns from ot her c i rc ui try . th e t y pe of is ola t io n is h i gh ly dep en den t on the sp ec ifi c a ppl ic ati on and m a y i n c l ud e dev ic es s u c h as res i s t ors , d i od es o r ev en ju m pers . r e f e r to f i gu re 3 0 -3 fo r m o re in f o rm at i o n. figure 30-3: t y p i cal conne ct ion for ics p ? p r o g ra mmin g v dd v pp v ss extern al d e vi ce to b e da t a clock v dd mc lr v ss icspda t icspclk * * * t o n or m al c o nn ec t i o n s * i sol a ti on dev ic es (as req u i r ed). p r og r am m i n g si gna ls p r ogr amm e d v dd http:///
? 2014 microchip technology inc. ds20005281a-page 207 mcp191 14/5 31 . 0 de ve l o pm en t s u p p o rt th e pic ? m i cr oco n tro l l e rs (m c u ) an d d s pi c ? dig i t a l s i g nal c ont roll ers (d sc ) are s upp orte d w i th a ful l rang e o f so f t w a re an d h a rdw a re d e v e lo pm ent too l s : ? i n t eg rate d d e v e l opm en t env i ro nm en t - m plab ? x i d e sof t w a r e ? c om pi le rs/as s e mb le rs/l ink e rs - m plab x c com p il er - m p asm tm as s e m b ler -m p l i n k tm o b j e c t li nk er/ mp l i b tm o b jec t li bra r ian - m plab a s s e m b le r/li nk er/l ibra rian fo r v a ri ous d e v i c e f a m ili es ? s i m u l at ors - m plab x sim sof t w a r e si m u la tor ?e m u l a t o r s - m plab real ice? i n -circ u i t em ula t or ? i n - c i rc uit d ebu gg ers/ progr amm e r s - m plab i cd 3 - p ick i t? 3 ? d ev ic e progra m m e rs - m plab p m 3 dev i c e prog ram m e r ? l ow -c os t d e m o n s tra t io n/d e vel o p m e n t bo ards , ev al uati o n kit s an d s t a r ter ki t s ? th i rd -p art y d e v e lo pm ent too l s 31. 1 m plab x int e grat ed devel opm e nt envi ronment sof t w a re th e m p lab x id e is a s i n g le , un ifi e d g r ap hic a l us er i n terf ac e for m i c r oc hi p an d th ird-p a rty so f t w a r e , an d ha rdw a re de ve lop m e n t to ol that runs on win d o w s ? , li nu x and m a c o s ? x. bas ed on the n e t b ean s id e, mp l a b x i d e i s an en t i r e l y ne w i d e w i th a ho s t o f f r ee s of t w a re c om pon ent s an d pl ug-i n s f or hi gh -perf o rm ance app li cat i on d e v e lo pm ent an d de bu ggi ng. m o v i n g be tw een tool s a nd up gra d in g from s o f twa re s i m u lato rs to ha rdware d e bu ggi n g an d pr ogra m m i n g to ols is si mp le w i th th e s eam le ss us er i n terf ac e. wi th c o m p le te pro j ec t ma nag em ent , v i s u a l cal l gra p hs , a co nfi gura b l e w a tch w i n dow and a fea t ure -ric h e d it or th at i n c l ud es cod e c o m p le tio n an d c ont ext me nus , m p lab x id e i s fl ex ibl e an d fri end ly eno u g h for n e w u s e r s. w i th t h e ab i l i t y to su pp o r t mu lt i p l e t o ol s on m ult ipl e proj ec t s w i th s i mu lt a ne ous d ebu ggi ng, m p lab x id e i s als o su it a b le fo r th e nee ds of ex pe rience d us ers . fe atu r e-r i c h e d ito r : ? c ol or s y n t ax h i gh lig hti n g ? s m art cod e c om pl eti on m ak es s ugg es tion s and p r o v id es hi n t s as yo u t y p e ? a u t om ati c c o d e f o rm atti ng bas ed on us er-d efi n ed ru les ? l iv e par s i n g u s er-fri end ly , c u st om iz abl e in terfa c e : ? f u lly c u s t om iz abl e i n te rfac e: t ool bar s, t ool bar bu tto ns, wi nd ow s , wi n dow p l a c em en t, et c. ? c al l g r aph w i n dow p r oj e c t - b as e d w o r k s p a c es : ? m ult i pl e p r oje c t s ? m ult i pl e tool s ? m ult i pl e c on f igu r ati ons ? s im ul ta ne ou s d e b u g g i n g se s s i o n s fi le h i s t ory an d bug t r ac k i ng : ? l oc al f i l e h i st or y fe a t ur e ? b u ilt- i n s u p port for bugz il la iss u e tra c k e r http:///
MCP19114/5 ds20005281a-page 208 ? 2014 microchip technology inc. 31. 2 m plab xc com p i l er s th e m p lab xc com p il ers are c o m p lete ansi c c om pil ers fo r all of mi cro c h i p? s 8, 16, and 32 -bit mc u a nd d s c d e v i c e s . the s e co mp il ers prov id e p o w e rfu l i n teg r ati o n c a p a b il iti e s , s upe rio r c ode o p timi z a t i on an d e a se of us e. m p lab xc c o m p il ers run on win d o w s , li n u x or ma c o s x . fo r e a sy s o u r ce lev e l de bug gi ng, the co mp il ers pro v id e d ebu g info rm atio n tha t i s op tim i z ed to th e m p la b x ide. th e fre e m p lab xc c o m p il er ed iti ons su pp ort al l d e vi ce s an d c o m m and s, w ith n o tim e or me mo ry re stri ct ion s , an d of fer su f f i c i ent c o d e opti m i z a t io n for m o s t ap pl ica t io ns . m p lab xc c o mp ile rs i nc l ud e a n as se mb le r , li nk er an d ut i l i t i e s . t h e as se mb le r ge n e r a t e s r e lo c a ta bl e o b j e ct fi le s tha t ca n th en b e arc hiv ed or li nk ed w i t h oth er r e l o ca t a b le o b j e ct f i le s an d ar c h i v e s to c r ea t e an e x ec ut abl e fi le. m p lab xc c o mpi l e r use s th e as se mb l e r t o p r od uc e i t s ob j e c t f i le . n o ta bl e f e at u r es o f th e a s s em ble r in cl ude : ? s u ppo rt fo r the en tire de vic e ins t ruc t i on s e t ? s u ppo rt fo r fix e d - poi nt and flo a ti ng-p o in t d a t a ? c o m m and -li ne i n te rfac e ? r i c h dire cti v e se t ? f l ex i bl e mac r o l an gua ge ? m plab x ide c o m p ati b i lit y 31. 3 m p a s m assembler th e mp asm as se mb ler is a full -fea ture d, un ive r sa l m a c r o a s s e m b le r fo r pic 1 0 / 12 /16/ 18 mc u s . th e m p asm as se mb ler g ene rates re loc a t abl e ob jec t fi le s fo r th e m p link o b jec t l i nk er , int e l ? s t an da rd h e x fi le s, m ap file s to det a i l m e m o ry us age a n d s y m b o l re ferenc e, a b s o lu te lst fil e s th at con t ai n sou r ce l i ne s a nd g ene rate d m ach in e co de , and c o f f fil es for d ebu ggi ng. th e m p asm as s e m b le r feat ure s i n c l ud e: ? in teg rati on into m p lab x i d e pro j ec t s ? u s e r-d efin ed ma cro s t o s t rea m l i ne as se mb l y co d e ? c o ndi tion al as se mb ly for m u l t ip urpo se s our ce fil e s ? d i r ect i v e s tha t al low c o m p l e te co ntrol o v er the a s s e m b ly pr oce s s 31. 4 m plink object li nker / mplib object l i brari a n th e m p lin k o b je ct l i nk er c o m b in es re loca t a bl e ob je ct s cre a te d by the mp asm a s s e m b le r . it c an l i n k re loc a t a bl e ob je ct s fro m p rec om pi led li brari e s , us in g di rec t iv es fro m a li nk er s c ri pt. th e mpl i b o b je ct li bra r ian m a n age s th e cre a ti on an d m odi fic a ti on of lib rary files o f p r eco m p i l ed cod e . whe n a rou t in e from a l i bra r y is c a l l ed fro m a so urc e f ile , o n l y th e m odu les tha t co nt a i n t hat ro uti n e w i ll b e li nk ed i n w i t h t he ap pli c a t ion . this all ow s la rge li brar ies t o b e us ed ef fici e n tl y i n m a n y d i f f eren t a ppl ic atio ns . th e o b je ct lin ke r/li brary fe atu r es inc l u de: ? e f f ic ie nt l i nk in g o f s i n g le li bra r ies i n st ead of ma ny s m a lle r fi les ? e n han ce d c ode ma in t a i nab ili ty by grou pi ng re late d m o d u le s t oge the r ? f l ex i bl e c r ea tio n of li brari es w i th ea sy mo dul e li s t i n g, r e pl ac e m e nt , de l et i on an d ex tr a c t i o n 31. 5 m plab assembl er , li nker and li brar ian for v a r i ou s devi ce f a mi lie s m p lab as se mb ler p r od uc es re lo cat abl e m a c h in e c ode fro m sy mb oli c as se mb ly la ngu age fo r pic 2 4, pic3 2 a n d d s pic dsc d e vi ce s . mpl ab xc co mp i l e r us es t he as se mb ler to pro duc e it s o bj ect fi le. th e as s e m b le r ge ne rates re lo cat abl e obj ec t fi les t hat ca n th en be arc h i v e d o r li nk ed w i th ot her rel o ca t a b l e ob ject fi les a nd a r ch iv es to c r ea te an e x e c u t ab le f ile . n ot abl e fe atu r es of t he a s s e m b l e r i n c l ud e: ? s u ppo rt fo r the en tire dev ic e i n s t ruc t io n s e t ? s u ppo rt fo r fix e d - poi nt a n d flo a ti ng-p o in t da t a ? c om m and -li ne i n te rfac e ? r ic h dire cti v e se t ? f l ex i bl e m ac r o l ang ua ge ? m plab x ide c o m p ati b i lity http:///
? 2014 microchip technology inc. ds20005281a-page 209 mcp191 14/5 31. 6 m plab x sim s o f t ware simul a tor th e m p lab x sim sof t w a r e si m u l a to r all o ws c o d e de v e l o p m e n t i n a p c - h o s t e d en v ir o nm en t b y si mu la t - in g t h e p i c mc u s a n d ds p i c d s c s on an in st r u ct i o n l e v e l. on an y g i v en ins t ruc t io n, the dat a ar eas c an b e e x am in ed o r mo difi ed a nd s t im ul i c an be app lie d fro m a co mp rehe ns iv e s t im ul us co ntrol l e r . r e g i s t ers c an b e l ogg ed to f ile s f o r fu rthe r run - tim e ana ly si s. t he trac e b uf f er and l ogi c an aly z e r d i s pla y ex ten d the po w er of th e s i m u la tor t o rec o rd and trac k p r og ram exe c u t io n, a c ti ons on i/o , mo st pe riph eral s an d int erna l regi ste r s. th e m p lab x sim sof t wa re sim u l a to r ful l y s u p port s s y m b o lic de bu ggi ng u s i ng the mpl ab xc c o m p i l ers , a nd t he m p asm a nd m p la b ass e m b l e rs. the so f t - wa re s i m u l a to r o f fe rs the fl ex ibi l i t y to de vel o p an d d ebu g c o d e o u t s ide of the ha rdw a r e l abo ratory e n v i - ro nm ent, m a k i ng i t a n e x c e l l en t, e c o nom ic al s o f t w a re d eve lo pm ent tool . 31. 7 m plab real ice in- c irc u it emulat or syst em the m p la b r e a l ic e in-c irc u it e m ulator system is m i crochip ? s nex t gene r atio n hi gh-speed emu l ator for m i crochip flas h d s c and mc u dev ices . it d ebugs and program s all 8, 16 and 32-bit m c u , and d s c devic es w i th the easy - to-us e , po w e rful graphic a l user interface of the m p l a b x id e. th e emu l at or i s con nec ted t o th e de sig n e ng i ne er ? s pc u s in g a h i g h - s pe ed u s b 2. 0 in te r f ac e an d i s con n e c te d to th e t a rg et w i th e i t h e r a co nn ect o r com p at ib le wit h i n - c i r cu it d ebu gg er sy ste m s ( r j- 1 1 ) or w i th t h e n e w hi gh- sp eed , no ise t o l e r a n t , lo w - v o ltag e d i ffe re nt ial si gn al ( l v d s ) i n t e r c on ne c t i o n (c a t 5 ) . the em ulator is field upgradeabl e throug h future firm- w a re dow nloads in m p la b x id e. mplab r eal ic e of fer s sig nifica nt a dvant ages over com petitive em ulators inc l uding full-speed emulatio n, run-time v ariable w a tches , trac e an alysi s, c o mple x breakpoint s , l ogic probes , a ruggediz ed probe i n ter f a c e and l ong (up to three m e ters) interconnec tion cable s . 31. 8 m plab i cd 3 in- c ir cuit debu gger syst em th e m p lab i c d 3 in -c ircu it d e bu gge r sys t em i s m i c r oc hip ? s mo st c o s t -ef f ec tive , hi gh -spe ed h a rdw a re de bu gge r/pro g ram m e r for m i c r oc hip fla s h d s c an d m c u de vi ce s. it de bug s and p r ogra ms pic fl as h m i c r oc ont rollers a nd ds pic d s c s w i th t he po w e rfu l , y e t eas y-t o -us e grap hic a l us er int e rfa c e of the m p lab ide. th e mp lab ic d 3 in-c i r cu it d e b ugg er pro b e i s c onn ec ted to th e d e s i gn e ngi nee r ? s pc u s i ng a hi gh -sp eed u sb 2 . 0 in terf ac e and is c o n nec te d to th e t a rget w i th a c onn ec tor c o m p ati b l e w i th th e m p lab i cd 2 o r m p la b r e a l i c e sy st e m s ( r j- 1 1 ) . mp l a b ic d 3 su ppo rt s al l m p lab i c d 2 h ead ers . 31. 9 p i c kit 3 in- c ir cuit debugger / pr ogrammer th e m p lab pic k it 3 a llo w s de bug g in g an d pr ogra m m i n g of pic an d d s pic flas h mi croc on trol ler s at a m o s t af for dab le p r ic e p o in t us in g th e po w e rfu l gr aph ic al us er i n te rfac e of the mp lab i d e . th e m p lab pic k it 3 is c o n nected t o t he de si gn en gin e e r ? s pc usi n g a ful l -s pee d u s b in terfa c e a nd ca n b e c onn ec ted to th e t a rg et vi a a mi cro c hi p de bug (r j - 1 1 ) c onn ec tor (c om p a t i bl e w i th m p lab ic d 3 an d m p lab real ice). th e c onn ec tor u s e s two dev i c e i/ o p i n s an d t he r e se t l i ne to im ple m e n t i n -c irc u it de bug gin g an d i n -c irc u i t seri al prog ram m i ng? (ic sp?). 31. 10 mplab pm3 dev i ce progr a m m er th e m p lab p m 3 d e vi ce prog ram m e r is a uni ve rsa l , c e c o m p li ant d e v i c e pro g ra mm er w i t h pro g ram m a bl e v olt age ve rifi cat i on at v ddm i n and v dd m a x fo r m a x i m u m reli ab ili ty . it feat ures a l a rg e lc d d i sp la y (1 28 x 6 4 ) for m enu s an d erro r m e s s a ges , an d a m odu la r , d e t a ch abl e soc k e t as sem b l y to su ppo r t v a rio u s p a c k age ty pes . th e ic sp c a b l e a s s e m b l y i s i n cl ud ed as a s t a nda rd i t em . i n s t an d-al one m o de , th e mp l a b p m 3 d e vi ce p r og r a mme r ca n r e ad , v e r i f y a n d pr ogra m pic de vi ces w i thou t a pc c o nn ec tion . it ca n al so se t c ode pro t ec tio n i n th is mo de. the mpl ab pm 3 c onn ec t s to the ho st pc v i a an r s -2 32 or u sb ca bl e. th e m p lab pm 3 h as hi gh-s pe ed co mm un ica t io ns an d op tim i z e d al gor ithm s for qu ic k p r og ram m i ng of larg e m e m o ry de v i c e s , a nd i n c o rpo r ate s a n m m c c a rd fo r fil e s t ora ge and dat a a ppl ic ati ons . http:///
MCP19114/5 ds20005281a-page 210 ? 2014 microchip technology inc. 31. 1 1 demonst r at ion/ develo p m ent boar ds, eval uati on ki t s , and st a r t e r k i t s a w i de v a ri ety of d e m ons trat ion , de vel o p m e n t an d e v al ua tion boa rds for v a rio u s pi c m c u s a nd ds pic d s c s a llo w s qu ick app lic at ion d e ve lo pm ent on f u ll y fu nc tio nal sy st ems . m o s t bo ards in cl ude prot oty p in g a r eas fo r ad din g c u s t om c i rc uit r y a n d pro v id e a ppl ic ati on fir m w a re and s o u r ce c o d e for ex am in atio n an d mo di f i c a t i on . th e boa rds su ppo rt a v a rie t y of fea t ures , inc l ud ing l e d s , te mp eratu r e s ens ors , sw it che s , s pea ke rs, r s -23 2 i n terf ace s , l c d di sp lay s , p o ten t io met e rs a nd ad diti ona l eeprom m e m o ry . th e d e m onstrat ion and de vel o p m en t bo ard s c an b e us e d i n t e a c hi ng e n v i r on me n t s , f o r pr o t ot y p i n g c u st om c i rc uit s an d for l earn i ng a b o u t va rio u s m i c r oc ont roll er a ppl ic ati ons . in addi tio n t o th e p i c d e m? and dsp i c d e m? demo n str a t i on/ dev elop ment b oar d ser i es of c i rcu i t s , micr ochi p has a lin e of evalu a ti on ki t s an d demo n str a t i on so f t w a re f o r a nalo g fi lte r de sign, k ee l oq ? se cu rity ics , ca n, ir d a ? , pow e r s mart bat ter y man age ment , s e e v al ? ev al uat ion sy st em, si gma- d e lt a a d c , fl ow r ate sen s ing , p l us many mor e. al so ava i l abl e are st a r ter k i t s th at c ont ain ev eryt hin g n eed ed to e x p eri enc e t he sp eci f ie d d ev i c e. t his u s u all y i nc l ud es a s i ng le a ppl ic ati on a nd deb ug c ap abi li ty , al l o n on e b oard. c h eck th e m i c r oc hi p w eb p a ge ( www .m i c ro c h i p . c o m ) fo r th e c o m p le te list o f de mo ns trati o n , de ve lop m e n t an d ev al u a t i on ki ts. 31. 12 thi rd- p art y devel opment t ools m i c r oc hip al so of fer s a gre at co lle cti on of too l s from th ird- p art y v end ors . the s e t ool s a re ca refu ll y s ele cte d to of fer goo d v a lu e a nd uni que fun c ti on ali t y . ? d ev ic e pr ogra m m e rs an d ga n g pro g ram m e rs fr o m com p a n i e s, su ch as s o f t l og an d c c s ? s oft w a r e t o o l s f r om c o mpan ie s , s u c h a s gi mp e l a n d t r ac e s y st em s ? p r o toc o l a nal yz er s fr o m c o m p a n ie s, su ch as sa lea e a nd t o t a l ph as e ? d em on str atio n bo ard s fro m co mp ani es , su ch as m i k r oel e kt roni ka , d i g ile nt ? a n d ol im ex ? e m b e dde d eth e rne t so luti on s fr om co mp ani es , s u c h as ez w e b l y nx , wi zne t an d ipl ogi ka ? http:///
? 2014 microchip technology inc. ds20005281a-page 211 mcp191 14/5 3 2 .0 p a ckaging informatio n 32.1 package marking information pin 1 pin 1 example 2 4 -le ad q f n (4x 4 x 0 .9 m m ) (m c p 191 14 only ) 191 1 4 e/m j ^^ 14 12 256 3 e le gen d : xx. ..x cu sto m e r-sp e c i fi c i n fo rma t ion y y e a r c ode (la s t dig i t of c a l end ar y ear ) yy y e ar c ode (la s t 2 d i gi t s of c a l end ar y e a r ) ww w e e k c o d e (w e e k of j a n uary 1 is w eek ? 01? ) n n n al pha nu me ric trac ea bil i ty co de pb -free je d e c des ig nato r fo r ma tte t i n (sn) * th i s pac ka ge is p b - f r e e. t h e p b - f r e e je d e c de si g n a t or ( ) c a n be fou nd o n t he o u te r p a c k agi ng for this p a ck ag e. note : i n t he ev en t the fu ll m i c r oc hip p a rt nu mb er ca nn ot be m a rk ed o n one l i n e , it w i l l be carr ied o v e r to t he ne xt li ne , t hus l i m i ti ng th e num be r o f av ail abl e c hara c t e rs for c u s t om er- s pe ci fic in form ati o n . 3 e 3 e pin 1 pin 1 example 28 -lea d q f n (5 x5x 0 . 9 m m ) (m c p 19 1 1 5 onl y) 19 1 1 5 e/m q ^^ 14 12256 3 e http:///
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? 2014 microchip technology inc. ds20005281a-page 213 MCP19114/5 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging http:///
MCP19114/5 ds20005281a-page 214 ? 2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging http:///
? 2014 microchip technology inc. ds20005281a-page 215 MCP19114/5 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging http:///
MCP19114/5 ds20005281a-page 216 ? 2014 microchip technology inc. 28-lead plastic quad flat, no lead package (mq) ? 5x5 mm body [qfn] land pattern with 0.55 mm contact length note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-2140a http:///
? 2014 microchip technology inc. ds20005281a-page 217 mcp191 14/5 ap pe ndix a: re vis i o n his t ory revi sio n a (march 2014) ? original release of this document. http:///
MCP19114/5 ds20005281a-page 218 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 219 mcp191 14/5 inde x a a/ d sp e c if ic a t io n s . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 3 , 5 , 3 5 a / d conver sion. see ad c ab econ re g i s te r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 9 ab s o lu t e m a x i m u m ra tin g s .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 2 2 ac ch a r a c te r i s t ic s . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 3 0 ac k st at st a t u s f l a g . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 7 7 adc .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 5 1 0 - b i t re su lt fo r m a t . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 7 a cquisit i on requirem ent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 as so c i a t e d re g i ste r s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 3 bl o ck dia g r a m .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 5 ca lc u l a t in g ac q u i si ti o n tim e . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 1 chann el selec t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 co n f ig u r a t i o n . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 6 co n f ig u r in g in te r r u p t . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 8 co n v e r si o n clo ck .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 6 conv ersion proc edure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 i n t e r nal sam p ling s wit ch (r ss ) i m pedanc e . . . . . . . . . . . . . . 131 in t e r r u p t s .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 7 op e r a tio n . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 8 op e r a tio n du r i n g sl e e p .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 8 po r t co n fig u r a t io n . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 6 re g i s t e r de fi n i ti o n s . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 9 require ment s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 s ource i m pedance (r s ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 1 tim i n g dia g r a m ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 3 6 adcon0 r e g i s t e r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 5 7 , 1 2 9 adcon1 r e g i s t e r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 0 adre sh r e g i s t e r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 0 adre sl re g i s t e r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 0 an a l o g bl o c ks e n a b l e co n tr o l. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 9 er r o r a m p l i fie r d i s a b l e .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 9 a nalog p e ripheral co nt rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 pwm s te e r in g .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 8 s e condary cur r ent pos i t i ve sens e p u l l -up . . . . . . . . . . . . . . . . . 48 a nalog-t o - digi t al conv ert e r. see ad c ans e l a re g i ste r . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 1 2 ans e l b re g i ste r . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 1 7 a ppli c at ion diagrams m c p19114 b oost q uasi-res onant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 m c p19114 cuk ? sy nchronous p o sit i ve o u t p ut . . . . . . . . . . 11 a ssem b l e r m p as m as se m b le r . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 0 8 b b ench t e s t ing sy ste m . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 5 7 bf . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 7 9 st a t u s f l a g . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 7 7 bf s ta t u s fla g . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 7 9 b l o ck diagrams adc . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 2 5 adc tr a n s f e r fu n cti o n . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 3 2 a nalog i nput mod e l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 b aud ra t e g e n e rat o r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 capt ure mode o perat i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 com pare mode o perat i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 i nt er r upt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 m c p19114 / 5 f l yb ack syn chronous q uasi-res o nant . 1 0 m i cro co n t r o lle r co r e .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 1 2 ms sp ( i 2 c mas t er mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 53 ms sp ( i 2 c slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 54 on - c h i p re se t c i r cu i t . .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. ... . 8 3 p u lse-w i dt h m odul at ion ( p w m ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 rec o mm ended mclr c i r c u i t . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. ... 84 time r 0 . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 1 3 5 tim e r 1 . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 1 3 7 tim e r 2 . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 1 4 1 w a t chdog t i m e r wit h shared pr escale . . . . . . . . . . . . . . . . . . . . 101 b r o w n - o u t r e se t ( b o r ) . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. 8 5 c c com p i l ers m p l a b xc .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 2 0 8 calibrat i on w o rd regist ers c a l w d 1 ( c a l ib r a ti o n w o r d 1 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 5 9 cal w d1 0 ( c a l i b r a t i o n wo r d 1 0 ) .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 6 6 c a l w d 2 ( c a l ib r a ti o n w o r d 2 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 0 c a l w d 3 ( c a l ib r a ti o n w o r d 3 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 1 c a l w d 4 ( c a l ib r a ti o n w o r d 4 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 1 c a l w d 5 ( c a l ib r a ti o n w o r d 5 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 2 c a l w d 6 ( c a l ib r a ti o n w o r d 6 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 2 c a l w d 7 ( c a l ib r a ti o n w o r d 7 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 3 c a l w d 8 ( c a l ib r a ti o n w o r d 8 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 4 c a l w d 9 ( c a l ib r a ti o n w o r d 9 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 6 5 cap t ure mode blo ck dia g r a m .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 1 4 7 cap t ure/ com pare ( ccd) module c a p tu r e m o d e .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 1 4 7 c c p1 i f .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 1 4 7 c c x pi n c o n f i g u r a t io n . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 1 4 7 p r e sc a le r . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 1 4 7 s o ft w a r e in t e r r u p t .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 1 4 7 t i mer 1 m ode s e lect ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 com pare mode c c p1 i f .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 1 4 8 cm p x pin co n f ig u r a t i o n . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 1 4 8 s o ft w a r e in t e r r u p t .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 1 4 8 s pecial e vent t r igger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 t i mer 1 m ode s e lect ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 re g i s t e r . . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 1 4 9 cc dcon re g i s t e r .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 1 4 9 c l o c k s w i t c h in g . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 8 2 cod e e xample i n d i r e ct a d d r e ss i n g .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. 7 8 cod e e xamples a/ d co n ve r si o n .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 1 2 8 a ssi g n i n g pr e s ca l e r to ti m e r 0 .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 1 3 6 a ssi g n i n g pr e s ca l e r to w d t . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 1 3 6 in it ia liz in g port gpa . .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 1 0 9 s a ving st at us and w regist ers in ra m . . . . . . . . . . . . . . . . . . . . . 98 com p are mode blo ck dia g r a m .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 1 4 8 c o m p u t e d f u n ct i o n c a l l s .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. 7 7 co m p u t e d goto.. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. ... . 7 7 c o n f i g u r a t io n w o r d .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . 7 9 r e g i s t e r s a sso c i a t e d w i t h c l o ck so u r c e s . .. .. .. .. .. .. .. . . . 8 2 wit h w at chdog t i m er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 cu r r e n t s e n se . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . 1 9 cus t om er change not i f i c a t i on serv i c e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 cus t om er support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 http:///
MCP19114/5 ds20005281a-page 220 ? 2014 microchip technology inc. d data m e mory co r e re g i st e r s . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 9 s t a t us re g i st e r . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 6 9 g eneral p u rpose regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 m a p . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 7 1 o r ganizat i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 s p e c i a l fu n ct i o n re g i st e r s . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . 6 8 , 7 0 dc and a c char act e rist ic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 g r aphs and t ables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 de adcon r e g i s t e r . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 4 5 de sa tcon re g i st e r . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 4 1 desat u rat i on det e ct i on f o r q uas i - resonant o perat ion . . . . . . . 41 developm ent suppor t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 de vi ce ca lib r a t i o n .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 5 9 ca l w d1 ( c a lib r a ti o n wo r d 1 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 5 9 ca l w d1 0 ( c a lib r a tio n wo r d 1 0 ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 6 ca l w d2 ( c a lib r a ti o n wo r d 2 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 0 ca l w d3 ( c a lib r a ti o n wo r d 3 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 1 ca l w d4 ( c a lib r a ti o n wo r d 4 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 1 ca l w d5 ( c a lib r a ti o n wo r d 5 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 2 ca l w d6 ( c a lib r a ti o n wo r d 6 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 2 ca l w d7 ( c a lib r a ti o n wo r d 7 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 3 ca l w d8 ( c a lib r a ti o n wo r d 8 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 4 ca l w d9 ( c a lib r a ti o n wo r d 9 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 5 de vi ce co n f i g u r a t io n . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . 3 7 , 7 9 code prot ect i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 co n f i g u r a t io n w o r d .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 7 9 i d l o c a tio n s . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 8 0 wr it e p r o t e ctio n . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 8 0 de v i c e ov e rv i e w .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 9 dig it a l ele ctr ic a l ch a r a ct e r i s t ic s . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 2 9 dir e ct ad d r e ss i n g . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 7 8 dr iv e r co n t r o l cir c u i t r y . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 2 0 e e l e ctr ic a l ch a r a cte r i st ic s . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 2 2 e r r a t a .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 7 ex t e rnal clock t i m i n g . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 3 0 t i m i ng requirem ent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 f f e a t u r e s .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 1 i 2 c i n te r f a c e . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 5 3 m i cr o co n t r o ll e r . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 1 t i m e r0 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 t i m e r1 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 f ile s e lec t reg i s t er. se e fs r f i r m wa r e i n s t r u ct io n s . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 9 5 f l as h p r ogram m e mor y co n tr o l .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 3 o perat ion during code p r ot ect . . . . . . . . . . . . . . . . . . . . . . . . . 107 o perat ion during w r it e prot ect . . . . . . . . . . . . . . . . . . . . . . . . . 107 p r o te ctio n ag a i n st s p u r io u s wr i te . .. .. .. .. .. .. .. ... .. 1 0 7 re g i ste r s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 4 reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 wr it in g t o .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 7 fs r re g i ste r . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 7 7 g g eneral p u rpose regist er. se e gp r gp r re g i ste r . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 8 i i/ o po r t s . .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 0 9 i 2 c i n terf a ce fe a t u r e s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 3 i 2 c mode (m ssp ) ac knowledge sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ac knowledge sequenc e t i ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 81 as so ci a t e d r e g i s t e r s . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . 1 8 7 b u s collis ion during a repeat ed st art condit i on . . . . . . . . . . . . . . . . . . . 1 85 during a s t art c ondi t i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 83 during a s t op condit i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 e f f e c t s o f a re se t . .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 8 2 i 2 c clo ck ra t e w/b r g.. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 8 8 m a s t e r m o d e .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 4 clo ck a r b i tr a t io n . .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 7 4 op e r a ti o n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 4 re ce p t io n . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. 1 7 9 repeat ed s t ar t condit i on t i m i ng . . . . . . . . . . . . . . . . . . . . . 176 st art condit i o n t i ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 t r a n sm i s si o n . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 7 7 multi-mas t er com m unic a tion, b u s collis ion and arbit r at ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 82 m u lti- m a s t e r m o d e .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 8 2 op e r a ti o n . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 6 ov e r v i e w .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 4 read/ w r it e bit i n f o rm at ion (r/ w bi t ) .. .. .. .. .. .. . . . . . . . . . . . . 1 5 8 slave m ode 1 0 - b i t ad d r e s s r e c e p t i o n . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 6 8 b u s collis ion . .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 164 c l o c k st r e t c h i n g .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . 1 7 2 c l o c k sy n c h r o n i z a ti o n . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 7 2 g e neral c a l l addres s support . . . . . . . . . . . . . . . . . . . . . . . . . . 1 73 op e r a ti o n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 8 ss pm sk 1 r e g i s t e r . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 7 3 t r a n s m i s s i o n . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 6 4 sleep o perat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 st op c ondi t i on t i ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 i c l e b c o n re g i s te r .. ... .. .. .. .. .. .. .. .. .. ... .. . . .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 3 i c oacon re g i s t e r .. .. ... .. .. .. .. .............................................. 4 2 i n - cir c u it s e r i a l p r o g r a m m i n g ( i cs p) .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . 2 0 5 c o m m o n pr o g r a m m i n g i n te r f a c e s .. .. .. .. .. .. .. .. . . . . . . . . . . . . 2 0 5 in d f r e g i s t e r .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 7 7 i n d i r e c t a d d r e s s i n g .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 7 7 , 7 8 i n p u t .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 2 o v erv o l t age lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 t yp e .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 1 3 underv o l t age lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 i n s t r u ct io n f o r m a t .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 5 in s t r u ct i o n se t . .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 5 ad d l w . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 7 ad d w f . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 7 an d l w . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 7 an d w f . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 7 b c f . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 7 bs f . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 7 b tfs c . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 7 b tfs s . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 8 ca l l .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 9 8 c l r f .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 9 8 cl rw .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 9 8 c l r w d t .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 9 8 com f .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 8 http:///
? 2014 microchip technology inc. ds20005281a-page 221 mcp191 14/5 de cf . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 8 de cfs z . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 g oto . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 i ncf . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 i ncfs z .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 i orl w . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 i orwf . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 m ov f . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 0 m ov l w .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 0 m ov w f . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 0 nop . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 0 re tfi e .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 1 re tl w . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 1 re turn .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 1 rl f . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 1 rrf .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 s l ee p . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 s u bl w . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 s u bw f . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 s u m m a r y ta b l e .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 6 s w a p f .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 x o rl w . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 x orwf .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 3 intcon register ................................................................93 internal sa mpling swit c h ( r ss ) i m pe dance . . . . . . . . . . . . . . . . . . . . . . 1 3 1 i n te r n e t a d d r e s s . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 2 5 i n t e rrupt -on-change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 9 a s s o c i a t e d re g i s te r s .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 1 cl e a r i n g in t e r r u p t fl a g s . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 1 9 enabling t he module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 9 i ndividual pin co nf igurat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 9 o p e r a t io n i n s l e e p .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 1 9 re g i s t e r s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 0 i n t e rrupt s a d c .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 8 a s s o c i a t e d re g i s te r s .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 8 co n f ig u r a t io n wo r d w/ clo ck so u r ce s . .. .. .. .. ... .. .. .. .. .. .. 8 2 co n t e x t s a v i n g . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 8 co n t r o l re g i st e r s . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 3 g p a 2 /i n t . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 1 t i m e r 0 .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 6 t i m e r 1 .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 8 i o ca re g i st e r .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 0 i o cb re g i st e r .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 0 l leading e dge b l anking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 l i n e a r re g u l a to r s . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 9 m magnet ic d e sat u rat i on det e c t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mast er syn chronous s e rial por t . se e ms sp mclr .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 4 i n te r n a l . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 4 mem o ry o r ganizat i on ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 da t a .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 8 p r o g r a m . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 7 m i c r o c h i p in t e r n e t we b si te .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 2 5 mode and r f b m u x cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 m o de c o n re g i s t e r .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 1 m os f et .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 1 7 driv er dead t i me . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 progra m m abl e dead t i m e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 undervolt age loc kout s e lect ion . . . . . . . . . . . . . . . . . . . . . . . . . 49 g a t e driver enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 m p l a b a sse m b l e r , l i n ke r , l i b r a r ia n . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 2 0 8 mp lab i cd 3 i n - circuit debugger s yst em . . . . . . . . . . . . . . . . . . . . . . 209 mp lab i n t egrat ed developm ent env i ro nment s o f t ware . . 207 m p l a b p m 3 d e vi ce pr o g r a m m e r . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 2 0 9 m p l a b r e al ic e i n - c i r c u i t e m u l a t o r s y s t e m .. .. .. .. .. .. .. .. . 2 0 9 m p l a b x si m so ft w a r e s i m u l a t o r . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 2 0 9 m p l in k o b j e ct l i n k e r /m pl i b o b je ct l i b r a r i a n . .. .. .. .. .. .. .. . 2 0 8 m s sp .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 1 5 3 a r b i tr a t io n . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. 1 5 5 baud rat e g enerat or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 block diagram ( i 2 c m a st er m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 block diagram ( i 2 c s l ave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 clo ck s t r e t c h i n g .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 5 5 i 2 c bu s t e r m s .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 5 6 i 2 c m a st e r m o d e .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 7 4 i 2 c m o d e .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. 1 5 4 i 2 c m ode o p erat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 56 i 2 c s l ave mode o perat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 58 ov e r vi e w .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 5 3 o op c o d e f i e l d d e sc r i p ti o n s .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 9 5 o p ti on_ r eg re g i ste r .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 7 6 o s cillat o r . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 81 as s o ci a t e d re g i st e r s . .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 8 2 ca li b r a t io n . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 8 1 delay u pon b a se f r equency change . . . . . . . . . . . . . . . . . . . . . . . . 82 delay u pon p o wer-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 delay u pon w a k e -up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 f r equency t uning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 i n te r n a l . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 8 1 o s ctune re g i st e r .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 8 1 ou tp u t d r i ve c i r cu i tr y .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 1 9 ov e r vo lta g e .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 9 ov con re g i st e r .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 3 9 ov ref c on re g i st e r .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . . 3 9 p r o te ctio n .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 9 t y p e . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 1 3 o u t put regulat ion ref erenc e v ol t age conf igurat ion . . . . . . . . . . 46 o v con re g i st e r .. .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 3 9 o v ervolt age loc kout i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ov r e f c o n r e g i st e r .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 3 9 p p a ck a g i n g .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 1 1 m a r k in g . . . . . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 2 1 1 s p e c i f ic a t i o n s .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 2 1 2 pc l . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 7 7 m o d i fy in g . .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 7 7 p c l a t h . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 7 7 p c on re g i st e r .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. 8 6 , 8 9 p e 1 re g i s te r .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 4 8 pe a k c u r r e n t m o d e .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 1 9 pi ckit 3 i n -circ u i t debugger/ p i ck it 3 in - cir c u i t p r o g r a m m e r . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 2 0 9 p ie 1 re g i st e r . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 9 4 p ie 2 re g i st e r . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 9 5 pin d i agr am 2 4 - p in qf n ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . 2 2 8 - p in qf n ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . 4 pinout des cript ion s u m m a r y . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 3 , 5 t a b l e .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 1 3 p i r1 re g i s t e r . . . . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 9 6 http:///
MCP19114/5 ds20005281a-page 222 ? 2014 microchip technology inc. p ir2 r e g i s t e r ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 9 7 p m a drh regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 105 pm adrl regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 104 pm co n1 re gi s t er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 105 p m con2 re g i s t e r . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 3 p m da th re g i st e r .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 4 p m da tl re g i st e r .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 4 po rt g p a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109, 119 a n se l a re g i s t e r .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 0 a s so ci a te d re g i s t e r s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 3 f u nct i ons and o u t put p r iorit i es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 i n t e rrupt -on-ch ange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ou t p u t pr io r i t y .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 0 regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109, 111 we a k p u ll- up s . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 9 po rt g p b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114, 119 a n se l b re g i s t e r .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 4 a s so ci a te d re g i s t e r s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 7 f u nct i ons and o u t put p r iorit i es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 i n t e rrupt -on-ch ange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ou t p u t pr io r i t y .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 5 regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114, 115 we a k p u ll- up s . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 4 power - down mode (sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a s so ci a te d re g i s t e r s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 0 p o we r - o n r e se t ( p o r ) . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 8 4 p o we r - u p tim e r ( p wrt) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 8 6 prim ary i nput c u rrent o f f set a d just . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 progr am mem o ry map and st ack (mc p19114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 o r ganizat i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 p r o te ctio n . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 8 0 p r o g r a m m i n g , de vi ce i n s t r u c t io n s .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 9 5 pulse- w i dt h m odulat ion cont rol logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 pulse- w i dt h m odulat ion. se e pwm p w m . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 3 4 a s so ci a te d re g i s t e r s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 4 5 cont rol logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 du t y cy cl e . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 4 5 enhanc ed m odule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 f i x ed f r equenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 op e r a t io n du r i n g s l e e p .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 4 5 ou t p u t . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 4 4 p e r i o d .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 4 4 requirem ent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 s i m p l i fi e d dia g r a m . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 4 4 st and-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 st andard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 s te e r in g . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 4 8 swit ching f r eque ncy syn chronizat i on m ode . . . . . . . . . . . . 143 t i m i n g dia g r a m .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 3 4 r read-m odif y- w rit e o p erat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 regist ers ab eco n (analog block e nable cont rol) . . . . . . . . . . . . . . . . . . . . 49 a dcon0 ( a / d co n t r o l 0 ) .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 2 9 ad c o n 0 ( a n a l o g - t o - d i g i t a l c o n t r o l ) .. .. .. .. .. .. .. .. .. .. . . . . . . 5 7 a dcon1 ( a / d co n t r o l 1 ) .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 3 0 a dres h ( a dc re s u lt hig h ) .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 3 0 a dres l ( a dc re s u lt l o w ) . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 1 3 0 a n se l a ( a n a l o g se le ct gp a) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 2 a n se l b ( a n a l o g se le ct gp b) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 7 ca l w d1 ( c a lib r a ti o n wo r d 1 ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 5 9 ca l w d1 0 ( c a lib r a tio n wo r d 1 0 ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 6 c a l w d 2 ( c a l i b r a t i o n w o r d 2 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 0 c a l w d 3 ( c a l i b r a t i o n w o r d 3 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 1 c a l w d 4 ( c a l i b r a t i o n w o r d 4 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 1 c a l w d 5 ( c a l i b r a t i o n w o r d 5 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 2 c a l w d 6 ( c a l i b r a t i o n w o r d 6 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 2 c a l w d 7 ( c a l i b r a t i o n w o r d 7 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 3 c a l w d 8 ( c a l i b r a t i o n w o r d 8 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 4 c a l w d 9 ( c a l i b r a t i o n w o r d 9 ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 5 ccdco n (dual c apt ure/ com pare cont ro l module) 149 c o n f ig ( c o n fi g u r a ti o n w o r d ) . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 7 9 dea dco n (driver dead t i m e cont rol) . . . . . . . . . . . . . . . . . . . . . . 45 des a t c o n (desat urat i o n com parat or con t rol) . . . . . . . 4 1 fs r ( f i l e s e le ct r e g i s t e r ) . . . . . . . .. .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . 7 7 g e n e r a l p u r p o se r e g i st e r . .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 6 8 i c l ebc o n (i nput curren t leading e dge b l anking co n t r o l) .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 4 3 i c o a co n ( i nput cur r ent o f f set a d just cont rol) . . . . . . . . 42 i n d f .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 7 i n tcon ( i n t e r r u p t co n t r o l ) . . . . . . .. .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . 9 3 i o ca (i nt errupt -on-change po rt g p a ) . . . . . . . . . . . . . . . . . . . 1 20 i o cb (i nt errupt -on-change po rt g p b ) . . . . . . . . . . . . . . . . . . . 1 20 mo de co n ( m ast e r/ slave and rf b m u x cont rol) . . . . 51 op ti on_ r eg ( op tio n ) .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 6 o s c t u n e ( o sc i l l a t o r tu n i n g ) . . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 8 1 o v co n (o ut put o v ervolt age com parat or c ont rol) . . . 3 9 o v re f c o n (o ut put o vervolt age d e t e c t level) . . . . . . . . 3 9 p c on ( p o w e r c o n t r o l) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. ... . . . . . . 8 6 , 8 9 pe 1 ( a nalog p e ripheral enable1 cont r o l ) . . . . . . . . . . . . . . . . . . 48 pi e1 (pe r ipheral i n t e r r upt enable 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 pi e2 (pe r ipheral i n t e r r upt enable 2). . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 pi r1 (peripher al i n t e rrupt f l ag 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 pi r2 (peripher al i n t e rrupt f l ag 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 pm adrh (p rogram m e mor y a ddres s high) . . . . 103, 105 pm adrl (p rogram m e mor y a ddress low ) . . . . . . 103, 104 pm co n1 ( p rogr am mem o ry cont r o l 1) . . . . . . . . . . . . 103, 105 pm co n2 ( p rogr am mem o ry cont r o l 2) . . . . . . . . . . . . . . . . . . . . 103 p m da th ( p r o g r a m m e m o r y da ta hig h ) . . . . . . .. .. .. .. .. .. 1 0 4 p m da tl ( p r o g r a m m e m o r y da ta l o w ) . .. .. .. ... . . . . . . . . . . 1 0 4 p o rtgp a . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 9 , 1 1 1 p o rtgp b . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 4 , 1 1 5 s l p crco n (s lope compens a t i on ramp cont rol) . . . . 44 s p e c ia l fu n cti o n ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. 6 8 spec ial regist ers sum m ar y b a n k 0 . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 2 b a n k 1 . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 3 b a n k 2 . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 4 b a n k 3 . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 5 ss pa dd ( m s sp addr ess and baud rat e 1) . . . . . . . . . . . 1 93 ss pa d d 2 ( m s sp ad d r e ss 2 ) . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 4 ss pc o n 1 ( s s p c o n t r o l 1 ) . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 0 ss pc o n 2 ( s s p c o n t r o l 2 ) . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 1 ss pc o n 3 ( s s p c o n t r o l 3 ) . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 2 ss pm sk ( s sp m a sk 1 ) . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 3 ss pm sk 1 ( s sp m a s k ) .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . 1 7 3 ss pm sk 2 ( s sp m a sk 2 ) . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 4 ss ps ta t ( s sp s t a t u s) . .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . 1 8 9 s t a t us .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 6 9 t 1 c o n ( t i m e r 1 c o n t r o l ) . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 3 8 t 2 c o n ( t i m e r 2 c o n t r o l ) . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 4 2 t r is gp a ( p or t g pa t r i - s t a t e ) .. .. .. .. .. .. .. .. .. . . . . 1 0 9 , 1 1 1 t r is gp b ( p or t g pb t r i - s t a t e ) .. .. .. .. .. .. .. .. .. . . . . 1 1 4 , 1 1 6 vi nco n (uvlo and o v lo com parat or con t rol) . . . . . . 37 vi no vlo (i nput o v ervolt age loc kout ) . . . . . . . . . . . . . . . . . . . . . . 3 8 vi nuvl o (i nput underv o l t age lockout ). . . . . . . . . . . . . . . . . . . . . 38 vr e f 2c o n (v re f2 volt age se t point ) . . . . . . . . . . . . . . . . . . . . . . 47 http:///
? 2014 microchip technology inc. ds20005281a-page 223 mcp191 14/5 vre f c o n (cur rent / v olt age regu l a t i on s e t point co n t r o l) .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 6 w p ug p a ( w eak pull-up p o rt g p a regist er) . . . . . . . . 112 w p ug p b ( w eak pull-up p o rt g p b regist er) . . . . . . . . 116 requirem ent s a /d ac q u i s i ti o n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 1 a / d co n v e r s i o n .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 5 e x t e r n a l clo c k , tim i n g .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 0 i /o, t i m i n g . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 1 p w m .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 4 reset , w a t c hdog t i mer , o scillat o r s t art - up t i mer and p o wer-u p t i mer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 t i m e r 0 e xte r n a l cl o c k . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 4 re s e ts . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 3 a s s o c i a te d re g i s t e rs .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 9 b r o w n - o u t . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 5 de t e r m i n i n g c a u se s . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 7 p o we r - o n .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 8 4 w a t c hdog t i mer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 s sleep wa ke - u p f r o m .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 9 wa ke - u p us in g i n te r r u p t s . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 0 0 slope compens at ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 s l p crcon regis t er . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 44 s o ft wa r e si m u la t o r ( m p l ab x s im ) .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 9 spec i a l ev ent t r i gge r capt ure/ com pare module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 s p e c i a l fu n ct i o n re g i st e r s ( s fr) . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 8 s s p a dd re g i s t e r .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 3 s s p a dd2 re g i s t e r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 4 s s p c on1 re g i st e r . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 0 s s p c on2 re g i st e r . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 1 s s p c on3 re g i st e r . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 2 s s p m s k re g i s te r .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 3 s s p m s k 1 re g i s te r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 3 s s p m s k 2 re g i s te r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 4 s s p ov .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 9 s s p ov s ta t u s fla g . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 9 s s p s t a t re g i ste r .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 8 9 r/w b i t . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 8 s ta c k . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 7 7 s ta r t- u p . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 0 st art - up s equence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 s t a t us re g i s te r .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 9 s y s t e m be n c h te s t in g .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. ...... 57 t t1con regist e r .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 8 t 2 co n re g i s t e r .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 4 2 t e mperat ure i ndicat o r module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 cir cu it op e r a t io n ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 3 t e m p e r a tu r e ou t p u t .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 3 t h e r m a l s p e cific a t io n s .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 8 t i m e r 0 . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 5 8-bit count er m ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8 - b i t ti m e r m o d e ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 5 a s so ci a te d re g i s t e r s .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 6 b l o ck dia g r a m .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 5 e x t e r n a l clo ck .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 6 requirem ent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ti m i n g .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 3 i n te r r u p t .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 6 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 fe a t u r e s . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 5 op e r a ti o n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 5 d u r i n g sl e e p .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 3 6 s o ft w a r e pr o g r a m m a b l e p r e s ca le r .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 5 sw i t ch i n g pr e s ca l e r . .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 3 6 t0 ck i . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 3 6 t m r 0 r e g i st e r .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 3 5 ti m e r 1 . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 7 as so ci a t e d r e g i s t e r s . .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 3 9 b l o ck dia g r a m .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 3 7 clo ck s o u r ce s e le ct io n . . . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 7 co n t r o l re g i st e r .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 3 8 ex te r n a l c l o ck t i m i n g .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 3 3 i n te r r u p t . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 8 m o d u l e . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 7 f e a tu r e s .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 3 7 op e r a ti o n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 7 d u r i n g sl e e p .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 3 8 p r e sca le r . .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 3 8 t m r 1 h r e g i st e r .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 3 7 t m r 1 l r e g i st e r .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 3 7 ti m e r 2 as so ci a t e d r e g i s t e r s . .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 4 2 b l o ck dia g r a m .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 4 1 co n t r o l re g i st e r .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 4 2 m o d u l e . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 4 1 f e a tu r e s .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 4 1 op e r a ti o n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 4 1 ti m e r s tim e r 1 ( t 1 c on) . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 7 tim e r 2 ( t 2 c on) . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 4 1 t i m i ng diagra m s a / d c o n ve r s i o n .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 3 6 ac knowledge sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 baud rat e g enerat or wit h clock arb i t r at i o n . . . . . . . . . . . . . 175 b r g re se t du e to sda a r b i tr a t io n during st art condit i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 b u s collision d u ring a repeat ed s t art c ondit ion ( c a s e 1 ) .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 8 5 b u s collision d u ring a repeat ed s t art c ondit ion ( c a s e 2 ) .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 8 5 b u s collision d u ring a s t art condit i on (s cl = 0) . . . . . 1 84 b u s collision d u ring a s t art condit i on (s da o n l y ) . . 1 83 b u s collis ion d u ring a s t op co ndi tion ( c as e 1) . . . . . . . 1 86 b u s collis ion d u ring a s t op co ndi tion ( c as e 2) . . . . . . . 1 86 b u s collision f o r t r ansm i t an d a cknowledge . . . . . . . . . . . 1 82 c l o ck sy n ch r o n i z a ti o n . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 1 7 2 fir st s t a r t bit . .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 7 5 i /o .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 1 i 2 c mas t er mode (7 or 1 0 -bit t r ansm i ssion) . . . . . . . . . . . . 178 i 2 c mas t er mode (7-b it recept ion) . . . . . . . . . . . . . . . . . . . . . . . . . . 180 in t pi n in t e r r u p t .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 9 2 po w e r - u p ti m e r . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 3 2 pulse - w i dt h modulat i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 repeat s t art c ondit i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 76 re se t . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 3 2 s ta rt- u p tim e r . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 2 st op c ondit i on r e ceive or t r ans mit m ode . . . . . . . . . . . . . . . 1 81 t i m e -out s equence c a se 1 . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 8 6 c a se 2 . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 8 7 c a se 3 . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 8 7 t i m e r 0 , e xte r n a l c l o ck .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 3 3 t i m e r 1 , e xte r n a l c l o ck .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 3 3 wa ke - u p fr o m i n te r r u p t . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 0 0 w a t c hdog t i mer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 http:///
MCP19114/5 ds20005281a-page 224 ? 2014 microchip technology inc. t i m i n g pa r a m e te r s y m b o l o g y . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 2 9 t r i s g p a .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 9 regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109, 111 t r i s g p b .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 4 regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114, 116 t y p i c a l pe r f o r m a n c e cu r v e s . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 5 3 u underv o l t age lockout i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 s e le ct io n fo r m o s f et dr iv e r . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 4 9 v v i ncon r e g i s t e r . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 3 7 v i nov l o re g i st e r . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 3 8 v i nuv l o re g i st e r . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 3 8 v re f2 volt age r e f e renc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 v r ef 2 c o n re g i ste r . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 4 7 v r ef c o n re g i ste r . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 4 6 w w a t c hdog t i mer . see wd t wcol . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 8 1 st at us f l ag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175, 177, 179, 181 wcol sta tu s f l a g . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 8 1 wdt .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 1 a s so ci a te d re g i s t e r s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 2 b l o ck dia g r a m .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 1 conf i gur at ion w o rd w/ w at chdog t i m er . . . . . . . . . . . . . . . . . . . 102 op e r a t io n . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 1 p e r i o d .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 1 p r o g r a m m in g co n s i d e r a t io n s . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 1 0 1 re se t . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 8 6 s witc h in g pr e sc a le r . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 3 6 wp ugpa r e g i s t e r . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 2 wp ugpb r e g i s t e r . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 6 www a d d r e ss . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 2 5 w w w , o n - l i n e s upport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 http:///
? 2014 microchip technology inc. ds20005281a-page 225 mcp191 14/5 the m i crochip w e b s i te m i c r oc hip pro v i des onl in e s upp ort v i a o u r w ww s i te at www .m ic roc h i p .c om . thi s w eb si te i s us ed as a m ean s to m ake fi les an d i nfo rma t io n e asi ly av ai lab l e to c u s t om ers . ac ce ss ib le by us ing yo ur f a v o rit e in tern et b r ow se r , th e w e b si te c o n t ai ns the foll ow in g in f o rm at i o n: ? prod uct su pport ? d a t a s hee t s and erra t a , a ppl ic atio n n ote s a nd sa mpl e p r og ram s , d es i gn re so urc es, us er ? s gui de s a nd hard w are sup po r t do c u m e n t s, la t e s t s o ft w a r e r e l e as es an d a r ch iv e d so ftw ar e ? g e n e ral t e chni cal suppo rt ? f r equ ent ly ask e d q u e s ti ons (f aq), tec h n i c a l s u p port req ues t s , o n li ne dis c u s s i o n gr oup s, mi cro c hi p c o n s ul t a n t pr o g r am m e m b er l i s t i n g ? b u s i ne ss o f mi cr och i p ? prod uc t se le cto r an d o r deri ng gui des , l ate st mi croc hi p p r es s re le ase s , li st i n g o f s e m in a r s a n d ev en ts, l is t i n gs of m i c r oc hip s ale s o f fi ce s, dis t rib uto rs and fac t ory re pres en t a ti ve s cus tome r c hange no tification se rv i c e m i c r oc hip ? s c u s t om er not ifi c at ion s e rv ice h e lp s kee p c u s t om ers cu rrent on m i c r oc hip prod uc t s . subs cri b e r s w il l r e ce iv e e- m a i l no t if i ca t io n w h en ev e r t h e r e ar e c han ge s, upd ate s , rev i s i on s or errat a re la ted to a s pec if ied p r odu ct fa mi ly o r d ev elo pm en t t ool o f inte res t . t o re g i s t er , ac ce ss t h e mi c r oc hi p w e b s i t e a t www .m ic roc h i p .c om . u nde r ?sup por t?, c lic k o n ?cu s to me r cha n g e no tifi ca tio n ? and fo llo w th e re gis t ra tion in s t ru c t ion s . cus tome r sup p o r t u s ers of mi cro c hi p p r od uct s c a n rec e i v e as si st a n c e th roug h s e v e ra l c han nel s: ? d is tri buto r or r epre s e n t a tiv e ? l oc al s a l e s offi ce ? f i e ld app l i c at ion eng i ne er (f ae) ? t ec hni ca l su ppo rt c us t o m er s sh oul d con t ac t the i r dis t rib uto r , re pres en t a ti ve o r fi eld ap pli c a t io n engi nee r (f ae) f o r s upp ort. loc al sa les of fic es are als o a v a ila bl e to hel p c u s t om ers . a lis tin g of s a l e s o f fi ce s an d lo ca tion s i s i n cl ud ed in th e b a c k o f th is doc um en t. t e c hnic a l s uppo r t is a vail a ble throug h the w e b si te at : http:/ /mic rochi p .co m /s uppo r t http:///
MCP19114/5 ds20005281a-page 226 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 227 mcp191 14/5 p r o d u c t i d e n t i fic a ti on sy stem to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern packag e t e mp eratu r e ran g e devi ce d evic e : mc p 1 91 14 : d i g i t al l y e n han ced p w m p o w e r a n al o g h i g h- s pee d c o ntr o l l e r mc p 1 91 15 : d i g i t al l y e n han ced p w m p o w e r a n al o g h i g h- s pee d c o ntr o l l e r t a pe an d r e el op ti o n : b l ank = s t a n d a rd p a ckag i ng (tu be) t = tape and reel t e m p e r atu r e ra n g e : e= - 4 0 ? c t o + 125 ? c ( e xt e nd ed ) p a cka ge : mj = 24- lea d pl a sti c qu ad fl a t, n o le ad p a ckag e - 4 x4x 0 . 9 m m b o dy ( q f n ) mq = 28- lea d pl a sti c qu ad fl a t, n o le ad p a ckag e - 5 x5x 0 . 9 m m b o dy ( q f n ) exam p l es: a) mc p191 14-e / m j : e x t ended t e mper at ure, 24 ld q f n 4x4 p a ck age b) mcp 191 14t -e / m j: t a pe and r eel , ex t ended t e m perat ure, 24 l d q f n 4x 4 p ac k age a) m c p1 91 15 -e/ m q : ex t ended t e m perat ure, 28 ld q f n 5x5 package b) m c p191 15t -e/ m q : t ape and reel, ex t ende d t e m perat ure, 28 ld q f n 5x5 package no te 1 : t ape a nd r e el id ent ifie r on ly appe ar s in th e catalog p a r t numb e r descr ipt ion . t h is i dent if ier is u s ed f o r ord er i ng pur pose s and is no t p r in ted on th e d e vice packag e . c h ec k w it h yo ur mi cr o c h i p s a le s of f i ce f o r p a c k a ge av ai lab i l i ty w i th th e t a pe a nd r eel opt ion . [x ] (1 ) t ap e an d reel option - http:///
MCP19114/5 ds20005281a-page 228 ? 2014 microchip technology inc. notes : http:///
? 2014 microchip technology inc. ds20005281a-page 229 i n f o r m a t i on c ont a i ne d in t h is p ubli c a t i on reg a r d in g d e v i ce ap pli c a t i ons a nd t he lik e is p r o v id ed on ly f o r yo ur c o n v e n ien c e an d m a y be su pe rs ed ed by u pda t e s . i t is y o u r r e s p o n s i bil i t y t o e n s u r e t h a t yo ur ap pl i c a t i o n me e t s wi t h yo ur sp ec if ic at io n s . mi c r o c h i p m akes n o r e pr e sen t a tion s or w a r r a n tie s of an y kin d w h eth e r ex pr e ss or im pl i e d , wr itte n o r o r al , s t a t u t or y or ot he r w is e , re la t e d t o t h e i n f o rm a t i o n, in c l u d i ng b u t not l i m i t e d t o it s c o nd i t i o n, qu al ity , pe r f orm a n c e, m e r chan t ab il i t y or fitn e ss for pu r p o s e . mi c r oc hip dis c l aim s al l lia bility ar is ing f r o m t h is i n f o r m a t i on an d it s us e. u s e o f m i cr oc hip de vic e s in li f e su pp ort a nd/ o r s a f e t y ap plic at io ns is e n t i r e ly at t he bu ye r ? s r i sk , a n d t h e buy er a g r e e s t o def e nd, ind e m n i f y and ho ld h a rm le ss m i c r o c h i p f r om a n y an d al l da ma ge s, c l ai ms , su it s , o r e x p ens es re s u lt ing f r om s u c h u s e . n o li ce ns es are conveyed, implicitly or otherwise, under any microchip intellectual property rights. t r ad emarks t he m i c r ochip name and l o g o , t he micr ochip logo, ds pi c, f l as hf lex , k ee l oq , k ee l oq logo, m p la b, p i c, p i cm icro, pi c s t a r t , pi c 32 logo, rf p i c , sst , ss t logo, s uperf l a s h and uni / o are regist ered t r ademark s of micr ochip t e chnology i n c o rporat ed in t he u. s. a. and ot her cou n t r ies. f i lt erlab, ham p shire, hi -t ech c, linear ac t i ve t hermist or , mt p , se ev al and t he em bedded cont r o l solut i ons com p any are r egist er ed t r a demark s of micr ochip t e c hnol o g y i n c o rporat ed in t he u. s. a. s ilicon s t or age t e chnology is a regist ered t r ademark of micr ochip t e chnology i n c. in ot her count ries. analog-f o r-t he-digit al age, app licat i on mae s t r o, body com, chipk i t , c h ipki t logo, codeg uard, ds pi cdem , d s pi c d e m . n e t , d s p i c w o r k s , d s sp ea k, e c an , e c onom oni t or, f a n s e n s e , h i - t ide , in - cir c u it se r i a l pro g ramm ing, i c s p , mindi, miw i , m p as m, m p f , mp lab cert if ied logo, m p li b, m p li nk , mt ouc h, o m nisc ient code generati on, p i cc, p i cc-18, p i cde m, p i c d e m . n et, p i ck it, pi ct ai l, re al i c e, rf lab , select m ode, sq i , s e rial q uad i / o , t o t a l e n dur anc e, t s ha r c, uniw indriv er , w i per loc k , z e na and z - s c ale are t r adem arks of m i crochip t e c hnol o g y i n c o rporat ed in t he u. s. a. and ot her cou n t r ies. sq t p is a s e rvice m a rk of mic r ochip t e chnology i n corpor at ed in the u.s . a . g e st i c and u l pp are regist ered t r adem arks of m i croc hi p t e c hnol o g y g e rm any i i g m bh & c o . kg , a s ubsidiary of micr ochip t e chnology i n c. , in ot her c ount ries . all ot her t r ademark s ment i o ned here i n are propert y of t h eir respe ct i ve com p ani es. ? 2 014 , micr ochip t e chnology i n c o rporat ed, pr i n t ed i n t h e u.s . a . , a ll right s r e se rv e d . pr i n t ed on rec ycled p aper . i s bn: 97 8-1-63276-03 4-0 no te th e fo l l o w i n g d e t a i l s o f th e co d e p r o t ecti o n featu r e o n m i cro c h i p d evi ces: ? m icr o chip pr oduct s m eet t he s pecif icat ion c ont ained in t heir p a r t icular mic r ochip dat a sheet . ? m icr o chip believes t hat i t s f a m ily of pr oduct s is one of t he mos t secure f a mili es of it s k i nd on t h e mar k et t oda y , when used i n t he i n t ended manne r and under norm a l condit i ons. ? t he re ar e dishones t and p o ssibly i llegal m e t hods used t o breach t he code prot ect i o n f e at ure . all of t hese met hods, t o our knowledge, requ i r e using t he micr ochip pr oduc t s in a m anner o u t s ide t he operat ing sp ecif icat ions cont ai ned in m i crochip? s dat a sheet s. m o st likely , t he p e rson doing s o is engaged i n t h ef t of int e ll ec t ual propert y . ? m icr o chip is will ing t o work wit h t he c u st om er who is con cerned about t he int e grit y of t hei r co de. ? n eit her micr ochip nor any ot he r sem i conduc t o r manuf act u rer can guarant e e t he sec u rit y of t h ei r code. co de prot ect i on does not mean t hat we are guarant eeing t he product as ?u nbreakable. ? code p r ot ec t i on i s c onst ant ly evolving. w e a t microc hip are co m m it t ed t o cont inuously improv i n g t he c ode prot ect i on f eat ur es of our product s. a t t e mpt s t o break micr ochip? s code prot ect i on f e at ure may be a violat i on of t he digit al mill enn i um copy right ac t . i f such act s all o w unaut horized acces s t o your sof t w ar e or ot her c opyright ed wor k, you ma y hav e a right t o su e f o r r e l i ef under t hat ac t . mi cr och i p r e cei v ed i s o/t s - 16 949 :20 09 cer t i f i cati o n f o r i t s w o rl dw i d e he adq ua rter s, d e si g n a nd w a fer fa bri ca t i o n fa ci l i t i es i n ch a ndl e r a nd t e m p e , a r i zo n a ; gr esh a m, or ego n a nd desi g n ce nte r s i n ca l i f o r n i a an d in di a. th e c o mpan y? s qu al i t y s ystem pr oce sses and pr oce dur es ar e fo r i t s p i c ? m c u s an d d sp i c ? dscs, k ee l oq ? co de ho pp i n g d e vi ce s, se r i a l eepro m s , m i cr o p e r ip h e r a ls , n o n vo l a t ile m e m o r y a n d an al og p r od ucts. in a ddi t i on, mi cr och i p? s q u a l i t y sys tem fo r the de si gn an d m anu fac t ur e of de vel o p m e n t s ystem s i s i s o 90 01 :200 0 c e rt i f i ed. quality management s ystem certifi e d b y dn v == is o / t s 169 49 == http:///
ds20005281a-page 230 ? 2014 microchip technology inc. ame r icas co rp o r ate o ffi ce 2355 w e s t chandler b l vd. chandler , a z 85224- 6199 t e l: 480-792- 7200 f a x: 480-792- 7277 t e chn i c a l su pport : ht tp: / / w ww .mic ro c h ip. c om/ support w e b a ddress : www .mic roc h ip.c om atlan t a dulut h , ga t e l: 678-957- 9614 f a x: 678-957- 1455 au sti n , t x t e l: 512-257- 3370 bo sto n w e st bor ough, ma t e l: 774-760- 0087 f a x: 774-760- 0088 ch i cag o ita s c a , il t e l: 630-285- 0071 f a x: 630-285- 0075 cl eve l a n d i ndepe ndence, o h t e l: 216-447- 0464 f a x: 216-447- 0643 dal l as addison , t x t e l: 972-818- 7423 f a x: 972-818- 2924 detro i t n o vi , m i t e l: 248-848- 4000 h ou s t o n, tx t e l: 281-894- 5983 i n d i an ap o l i s nobles ville, i n t e l: 317-773- 8323 f a x: 317-773- 5453 lo s a n ge l e s miss i o n v i ejo, ca t e l: 949-462- 9523 f a x: 949-462- 9608 ne w y o r k , ny t e l: 631-435- 6000 san j o se, c a t e l: 408-735- 91 10 c a na d a - t or ont o t e l: 905-673- 0699 f a x: 905-673- 6509 as ia/p acific asi a paci fi c o ffi ce s u it es 3707-14, 37t h f l oor t o wer 6, t he g a t e w a y har bour ci t y , k owloon hon g k ong t e l : 852-2401-1200 f a x: 85 2-2401-3431 au stral i a - syd n e y t e l : 61-2-9868-67 33 f a x: 61 -2-9868-6755 ch ina - bei j i n g t e l : 86-10-8569-7 000 f a x: 86 -10-8528-210 4 ch in a - ch e n g d u t e l : 86-28-8665-5 5 1 1 f a x: 86 -28-8665-788 9 c hin a - c h ongq ing t e l : 86-23-8980-9 588 f a x: 86 -23-8980-950 0 ch ina - han g z h o u t e l : 86-571-8792- 81 15 f a x: 86 -571-8792-81 16 c h in a - h o ng k o ng sa r t e l : 852-2401-1200 f a x: 85 2-2401-3431 ch in a - nan j in g t e l : 86-25-8473-2 460 f a x: 86 -25-8473-247 0 c hin a - q i ng da o t e l : 86-532-8502- 7355 f a x: 86 -532-8502-72 05 ch i n a - sh an g h ai t e l : 86-21-5407-5 533 f a x: 86 -21-5407-506 6 ch i n a - sh en yan g t e l : 86-24-2334-2 829 f a x: 86 -24-2334-239 3 ch i n a - sh en zh en t e l : 86-755-8864- 2200 f a x: 86 -755-8203-17 60 c h in a - w uha n t e l : 86-27-5980-5 300 f a x: 86 -27-5980-51 18 ch i n a - xi an t e l : 86-29-8833-7 252 f a x: 86 -29-8833-725 6 ch i n a - xi amen t e l : 86-592-2388138 f a x: 86 -592-2388130 c hin a - z huha i t e l: 8 6 -7 56 -3 210 040 f a x: 86 -7 56 -32 1 0 049 as ia/p a c ific i n d i a - ban g al o r e t e l: 91-80- 3090-4444 f a x: 91-80- 3090-4123 i n d i a - new delh i t e l: 91-1 1 -4160-8631 f a x: 91-1 1 - 4160-8632 i ndi a - p un e t e l: 91-20- 3019-1500 jap an - o s aka t e l: 81-6- 6152-7160 f a x: 81-6-6 152-9310 jap an - t o kyo t e l: 81-3- 6880- 3 770 f a x: 81-3-6 880-3771 ko rea - daeg u t e l: 82-53- 744-4301 f a x: 82-53- 744-4302 ko rea - seo u l t e l: 82-2- 554-7200 f a x: 82-2-5 58-5932 or 82-2-558 -5934 mal aysi a - ku al a l u m p u r t e l: 60-3- 6201-9857 f a x: 60-3-6 201-9859 mal aysi a - pen a n g t e l: 60-4- 227-8870 f a x: 60-4-2 27-4068 p h il ip pin e s - m a ni la t e l: 63-2- 634-9065 f a x: 63-2-6 34-9069 s i ng a por e t e l: 65-6334 -8870 f a x: 65-6334- 8850 t a i w an - hsin ch u t e l: 886-3- 5778-366 f a x: 886-3- 5770-955 t a i w a n - ka ohs i ung t e l: 886-7- 213-7830 t a iw a n - t a ip e i t e l: 886-2- 2508-8600 f a x: 886-2- 2508-0102 th a i l a nd - ba ngk o k t e l: 66-2- 694-1351 f a x: 66-2-6 94-1350 e urop e a u stri a - w e l s t e l: 43-7242-2244- 39 f a x: 43-7242-2244- 393 d e n m a r k - c op e nha ge n t e l: 45-4450-2828 f a x: 45-4485-2829 f r an ce - p ari s t e l: 33-1-69-53 -63-20 f a x: 33-1-69-30- 90-79 g e rman y - d u ssel d o rf t e l: 49-2129-37664 00 g e rman y - m u n i ch t e l: 49-89-627- 144-0 f a x: 49-89-627-14 4-44 ge r m a ny - pf or zh e i m t e l: 49-7231-42475 0 i t al y - m i l an t e l: 39-0331-74261 1 f a x: 39-0331-466781 i t al y - v en i ce t e l: 39-049-762528 6 n e th e r l a n d s - dru n en t e l: 31-416-690399 f a x: 31-416-690340 pol a nd - w a r s a w t e l: 48-22-3325737 s p a i n - ma d r i d t e l: 34-91-708- 08-90 f a x: 34-91-708-08 -91 s w ed en - sto ckh o l m t e l: 46-8-5090- 4654 u k - w o k i ng ha m t e l: 44-1 18-921- 5800 f a x: 44-1 18-921- 5820 w o rl dw id e sal e s and s e r v ic e 03/21/14 http:///

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